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Synopsys

Synopsys, November 28, 2023

Making the Right Connections – Taking the Guess Work out of DFT Connectivity Validation

System-on-Chip (SoC) designs continue to grow in both size and complexity in order to meet the ever-growing performance and power demands associated with modern technology.… Read More »Making the Right Connections – Taking the Guess Work out of DFT Connectivity Validation

Synopsys, November 14, 2023

Automated Constraints Promotion Methodology from IP to SoC for Complex Designs

IP cores require integration into top-level subsystems and/or SoCs. Writing constraints manually for top level design is prone to errors and difficult to verify and… Read More »Automated Constraints Promotion Methodology from IP to SoC for Complex Designs