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Cadence, November 2 2023

IR 2.0 – Building a New Paradigm for Power Integrity Design and Analysis

Power integrity (PI) is a major challenge for chip designers in the era of ubiquitous data, hyperconnectivity, and AI. Design size is exploding, and innovations in heterogenous integration are adding to PI complexity. These changes… IR 2.0 – Building a New Paradigm for Power Integrity Design and Analysis