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Aldec, August 31, 2023

Advanced Testbench for a Complex DUT

Functional simulation using an HDL testbench is the de facto method for proving functional correctness of FPGA designs. In this three-part webinar series, we will present a step-by-step approach on how to architect a testbench… Advanced Testbench for a Complex DUT

Aldec, May 5, 2022

FPGA Verification Architecture Optimization with UVVM

Presenter: Espen Tallaksen, CEO of EmLogic Thursday, May 5, 2022 Abstract: For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification… FPGA Verification Architecture Optimization with UVVM