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17th International MOS-AK Workshop, Silicon Valley
December 11, 2024 @ 9:00 am - 12:00 pm PST
Modeling of Systems and Parameter Extraction Working Group
| T_0 | MOS-AK Welcome and Opening Long Ma and Wladek Grabinski Keysight Technologies (US) and MOS-AK (EU) |
| T_1 | What’s New in Keysight Device Modeling 2025 Long Ma Keysight Technologies (US) |
| T_2 | Si2 Compact Model Coalition 2024 Updates Peter M. Lee CMC Chairman (US) |
| T_3 | OpenVAF – status update, ecosystem, and a roadmap Arpad Burmen FE Uni Ljubljana (SI) |
| T_4 | A Wrapper Model for ESD-FET Simulation and Analysis Harshit Agarwal IIT Jodhpur (IN) |
| T_5 | Compact Modelling of Memristors Toward Analog Neuromorphic Circuit Simulations Thomas Ratier, Jean-Charles, Delvenne, Denis Flandre, Leopold Van Brandt UC Louvain (B) |
| T_6 | Inductor Modeling and Generation Flow for Verified RFIC Layouts Using Open-Source PDKs Francisco Brito-Filho, Hugo Dias Gilo and Iranildo Alves Sales UFERSA (BR) |
| T_7 | Characterization and modelling of low-frequency noise in polysilicon thin-film source-gated transistors from subthreshold to saturation Qi Chen*, Valeriya Kilchytska, Eva Bestelink, Radu A. Sporea, Denis Flandre, Leopold Van Brandt ICTEAM, UCLouvain (B) |
| T_8 | Gm/ID-Based Analog Circuit Sizing Using Ngspice and Python Boris Murmann University of Hawaii (US) |