The IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in test, validation, yield, reliability, and security of microelectronic circuits and systems.
The symposium will take place on April 24-26, 2023, at the Hyatt Regency Mission Bay Spa & Marina, 1441 Quivira Road, San Diego, CA, USA.
The program includes keynotes, scientific paper presentations, short industrial application paper presentations, special sessions, and Innovative Practices sessions.
You are invited to participate and submit your contributions to VTS’23. The areas of interest include (but are not limited to) the following topics:
- Analog, Mixed-Signal, RF Test
- ATPG & Compression
- Silicon Debug
- Automotive Test & Safety
- Built-In Self-Test (BIST)
- Defect & Current Based Test
- Defect & Fault Tolerance
- Delay & Performance Test
- Design for Testability, Yield or Reliability
- Pre-silicon Design Verification & Validation
- Post-silicon Validation
- Embedded System & Board Test
- Embedded Test Methods
- Emerging Technologies Test and Reliability
- FPGA Test
- Fault Modeling and Simulation
- Hardware Security
|
- Low-Power IC Test
- Machine Learning in Test,Yield and Reliability
- Microsystems/MEMS/Sensors Test
- Memory Test and Repair
- On-Line Test & Error Correction
- Power & Thermal Issues in Test
- System-on-Chip (SOC) Test
- Test & Reliability of Biomedical Devices
- Test & Reliability of High-Speed I/O
- Test & Reliability of Machine Learning Systems
- Test Quality & Reliability
- Test Standards & Economics
- Test Resource Partitioning
- Transient & Soft Errors
- 2.5D, 3D & SiP Test
- Yield Optimization
|
Like this:
Like Loading...
Related
