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Accelerating DFT verification sign-off with the Questa DFT Verification Platform
October 8 @ 10:00 am - 3:00 pm PDT
Accelerating DFT verification sign-off with the Questa DFT Verification Platform
This seminar will update you on technologies and techniques you can adopt to increase your DFT verification productivity today. Specifically, we will cover:
Navigating the Growing Complexity of Design-for-Test and Evolving Verification Challenges
Revolutionizing Test Strategies to deliver reliable products into HPC, Automotive, Aerospace, Medical, and beyond
Agenda:
10:00 am – 10:25 am
Registration and check-in
Coffee and networking with your peers.
10:25 am – 10:30 am
Welcome/Intro
Harsh Patel | Sr. AE Manager, Functional Verification
10:30 am -11:15 am
Understanding and navigating the new challenges in Design-for-Test
Lee Harrison | Director of Product Marketing -Tessent
11:15 am – 12:00 noon
Accelerating verification closure with Siemens DFT tailored verification solutions
Jake Wiltgen | Director, IC Verification Solutions
12:00 noon – 12:30 pm
Lunch and networking
12:30 pm – 1:15 pm
Embracing a New Era in DFT: Addressing High Defect Coverage, Silent Data Errors, and Emerging Challenges
Lee Harrison | Director of Product Marketing -Tessent
1:15 pm – 2:00 pm
Increasing fault coverage with Siemens Functional Fault Grading solutions
Ann Keffer | Product Manager
2:00 pm – 3:00 pm
Wrap-up and networking
We look forward to seeing you!
Siemens Advanced Functional Verification Team