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ASYNC 2022 Summer School: Gate-level Design
June 13 @ 9:00 am - 1:00 pm PDT
The steering committee of the IEEE ASYNC symposium is organizing a summer school on asynchronous design. The goal of the school is to teach asynchronous chip design to students and practitioners interested in digital hardware design. Participants will learn how to design asynchronous circuits at the behavioral level, gate level, and physical design level using design automation tools and the Skywater 130 open-source PDK.
Registration: by May 10, 2022
Note that there are limited seats. We will notify you by May 20th. Video recordings of the sessions will be made available to all.
Format: Virtual (via Zoom), morning sessions, 9:00am to 1:00pm Eastern Time (US) (Time Zone -4:00 UTC)
Session 1. June 6: Behavioral design
Session 2. June 13: Gate-level design
Session 3. June 20: Physical design
(Please monitor this page frequently for updates)
Expected background: We will assume that attendees are familiar with basic logic design (level of an introductory logic design course that is taught at a University). We will also assume familiarity with introductory programming and scripting.