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Driving Low-Power Design with High-Level Synthesis

With the growth in computing at the edge driven by the explosion of battery-powered smart devices, designing for low power is mission-critical to product success. Numerous techniques, spanning all stages of design, are employed to reduce power. Since many of the low-power design techniques come at a cost in performance, the key design challenge continues… Read More »Driving Low-Power Design with High-Level Synthesis

Digital Engineering Best Practices for Aerospace & Defense

Register for this Cadence TECHTALK™ webinar, where senior director of solutions marketing Frank Schirrmeister will discuss how commercial electronics hardware companies use cutting-edge design techniques to ensure that their hardware/software designs work as intended prior to fabrication. This ensures that hardware is built right the first time, in an affordable, sustainable, and agilely modernizable fashion.… Read More »Digital Engineering Best Practices for Aerospace & Defense

Overcoming PCIe 6.0 System Integration and Pre-Silicon Validation Challenges

PCIe, the most popular interconnect in compute, AI and storage systems, is now offering faster data rate, higher performance, lower power and lower latency than the previous generation. Because of these reasons and the addition of PAM-4 signaling, challenges such as signal integrity, power integrity, implementation, IP integration and more must be considered when designing… Read More »Overcoming PCIe 6.0 System Integration and Pre-Silicon Validation Challenges

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