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Applications of Formal Verification

It is an exciting time to explore a career in the VLSI semiconductor sector, and we're here to help you gain clarity on buzz and provide information on educational options towards a successful entry to this field with long-term career prospects. Design Verification is one of the essential and most promising career options. In the… Read More »Applications of Formal Verification

Unleashing Innovation with UCIe​​​​​​​​​​​​​​

Exploring the Next Frontier in Chip Integration Webinar Agenda : Introduction to all UCIe layers Decrypting FLITs, PHY Trainings, Bring up flows FDI-RDI , main band and side band FLIT transfers etc. Implementation of Stacks-Arbiter, Retry mechanism & Retimer implementations Showcasing UCie FLIT transfer flow between multidies Enhancements done in UCIe 1.1 Who Should Attend:… Read More »Unleashing Innovation with UCIe​​​​​​​​​​​​​​

Synopsys VSO.ai Virtual Workshop

Virtual workshop with hands-on labs Achieving coverage closure continues to remain a challenge for customers and there is a growing need for a system to work autonomously to reach the target as quickly and cheaply as possible with the highest quality of results. The recently released Synopsys VSO.ai address this challenge in addition to inferring… Read More »Synopsys VSO.ai Virtual Workshop

Cadence Training: Cerebrus Intelligent Chip Explorer

Please join me, Cadence Training and Application Engineer Krishna Atreya, for this free technical Training Webinar. What Is the Webinar About? The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, machine learning-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and Cadence Cerebrus intelligently optimizes the Cadence digital full flow… Read More »Cadence Training: Cerebrus Intelligent Chip Explorer

Stratus HLS Automated Power Shutoff to Minimize Power and Retention Registers

Power Shutoff is a popular technique for saving power during functionally idle periods. Implementing Power Shutoff requires a detailed understanding of which resisters must be retained to enable bring-up from the power-off state. Identifying the minimal set of retention registers is challenging and grows more difficult with design complexity. This CadenceTECHTALK introduces a novel High-Level… Read More »Stratus HLS Automated Power Shutoff to Minimize Power and Retention Registers

FPGA Design Verification – Advanced Testbench Implementation

Abstract As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA teams are adopting advanced design verification… Read More »FPGA Design Verification – Advanced Testbench Implementation

Verisium Debug for UVM Testbench

Verisium Debug offers comprehensive debugging capabilities. From RTL and UVM testbench to UPF low-power designs, Cadence’s unified debugging platform helps users debug. In this webinar, users will learn about the available features in Verisium Debug for UVM testbench and use these unique capabilities to visualize and debug the UVM testbench. What you will learn Understand… Read More »Verisium Debug for UVM Testbench

FPGA Design Verification – Advanced Methods

Abstract As FPGA technology continues to evolve - to provide us with full-blown SoCs with CPU, GPU, and high-speed peripherals, for example, joining the traditional programmable logic area - design verification becomes increasingly challenging. Lab-based FPGA testing and bring-up alone are clearly insufficient, especially for safety-critical designs, and FPGA teams are adopting advanced design verification… Read More »FPGA Design Verification – Advanced Methods

Proactively Address Thermal Concerns in Advanced IC Packages

The heterogeneous integration of chips and chiplets in IC packages is all the rage as we face “More than Moore” performance challenges. While these innovative design practices successfully address performance goals, some design teams find that IC packages may overheat if they do not carefully plan for heat dissipation. This webinar will show how design… Read More »Proactively Address Thermal Concerns in Advanced IC Packages

The UCIe™ 1.1 Specification: Future Applications of Chiplets

Presenter: Dr. Debendra Das Sharma, UCIe Consortium Chairman and Intel Senior Fellow, Chief Architect of I/O Technology and Standards at Intel  The UCIe™ (Universal Chiplet Interconnect Express™) 1.1 Specification was released in August 2023, delivering valuable improvements to the chiplet ecosystem, extending reliability mechanisms to more protocols and supporting broader usage models. This webinar will provide… Read More »The UCIe™ 1.1 Specification: Future Applications of Chiplets

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