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Win The Tick to Trade Race by Root Causing Bugs Faster with the Latest Innovations In QuestaSim

Root causing RTL design or simulation testbench bugs can be tedious process, especially if just relying on traditional waveform viewing and debug. Also, it can be costly if more sophisticated debug ties up precious simulation resources during the debug process. ‌ Learn how the latest innovations in QuestaSim address these challenges by enabling full off-line… Read More »Win The Tick to Trade Race by Root Causing Bugs Faster with the Latest Innovations In QuestaSim

Streamline MMIC Design Efficiency with Intelligent Design Data Management

In the fast-evolving world of monolithic microwave integrated circuit (MMIC) design, meeting higher-frequency requirements is just the beginning. Are you seeking insights on achieving dimensional accuracy for both analog and RF components? Wondering about the automatic synchronization of schematics and layouts across various electronic design automation (EDA) tools? Trusted by hundreds of IC design organizations… Read More »Streamline MMIC Design Efficiency with Intelligent Design Data Management

Exploring the Advancement of Chiplet Technology and the Ecosystem

Semiconductor companies are making transistors smaller and cramming more into chips to meet the demands of today’s high-tech industries and applications. In fact, in a recent article from the Financial Times, technology industry consultants McKinsey forecast that semiconductors will become a trillion-dollar industry by the end of this decade. Even with this massive growth, manufacturers recognize the… Read More »Exploring the Advancement of Chiplet Technology and the Ecosystem

DVClub Europe – Formal Verification

13 days to go the next DVClub Europe meeting takes place on Tuesday 23rd April with a theme of "Formal Verification". Formal Verification can help you find bugs earlier in the design cycle and accelerate root cause analysis. But success with Formal requires the effective selection and implementation of the right formal technologies and methods. In this DVClub meeting… Read More »DVClub Europe – Formal Verification

The Era of Software-Defined Everything: Chiplets and Bespoke Silicon

From fintech to automotive, defense to healthcare, everyone wants bespoke computing platforms to build "software-defined solutions" that are differentiated in their respective markets. Sign up and save your spot for this special presentation. Overview With the advent of 3D ICs and heterogeneous semiconductor integration, mapping a system on a customized chip/hardware is accessible to "everyone.”… Read More »The Era of Software-Defined Everything: Chiplets and Bespoke Silicon

Improving Semiconductor Wafer Fabrication Process Efficiencies Using Ansys Solutions

Ansys Semiconductor Manufacturing Webinar Series: Part 1 of 3. Join us on Thursday, April 25th for an in-depth view of multi-physics simulation in the semiconductor fabrication process. Overview Accurate design and optimization of the semiconductor fabrication process/equipment for yield improvements and faster time-to-market require multiphysics simulation, which can address various physical interactions and phenomena. By… Read More »Improving Semiconductor Wafer Fabrication Process Efficiencies Using Ansys Solutions

AI-Driven EM-IR Design Closure

IR drop closure is becoming a major challenge for designers on advanced nodes. The number of violations at signoff has increased significantly, leading to longer turnaround time (TAT) or violations being waived. To solve this challenge, IR drop needs to be addressed early in the implementation phase with an automated IR prevention and fixing methodology.… Read More »AI-Driven EM-IR Design Closure