- This event has passed.
Design Methodology for Building Power Efficient RTL
April 12, 2022 @ 9:00 am - 12:30 pm PDT
The growth of semiconductor industry hinges on the fact that with every new generation, chips would have higher performance and consume less power. However, we are witnessing that scaling through Moore’s law does not automatically translate to efficiency gains in terms of energy anymore. That’s why regardless of the application area – networking, computation, or storage – power and energy consumption can make the difference between a differentiated product and a product that does not meet customer needs. In the 2020 survey by Wilson Research, power is now the #3 reason for design re-spins.
That brings power at the front and center in silicon design process. It is obvious that we cannot wait until the very end of their design cycle to try to fix power problems and it needs to be considered during the architecture and design phase. We need an effective hardware design methodology to deliver lowest power RTL IP and/or designs.
This seminar will highlight how power and energy metrics and optimization can predictably deliver the best quality RTL optimized for power. It will feature a combination of technical sessions and user case studies delivered by people who have adopted those best practices to build successful products.
10 min – Seminar Introduction and Customer Case Studies
30 min – Arm: Decarbonizing Compute Through Energy-Efficient IP Design
30 min – Fast-tracking low-power design with an early power methodology
30 min – Building Power Efficient Cisco Network Switches Through PowerPro Guidance, Early Tracking and Optimization
30 min – Fast and Accurate Power Analysis Using PowerPro – From IP to System
10 min – Closing Session
Technical Director, Physical Implementation
Pierre-Alexandre Bou-Ach is a Technical Director at Arm, originally from the south of France and now based in Trondheim, Norway.
He is helping the different Arm physical implementation teams worldwide with methodology and EDA strategy aspects, as well as being the physical implementation technical authority for the Total Compute program.
He started his career at STMicroelectronics inCrolles, France, working on high-performance Arm Cortex CPU implementations. He then joined Arm in 2013, working initially in the GPU group, notably as a physical implementation lead on several Mali GPU products and also as a methodology team lead for GPU physical design.
Udupi Harisharan is a senior engineering leader who works on power analysis and power optimization throughout the design and development flow of the Data Center Asics at Cisco. He looks at profiling and modeling the power/energy usage of the design and improving the energy efficiency via various methods that target logic and memories. He is also involved in signing of the power in terms of thermal dissipation as well as Chip/System IR analysis. He has been working at cisco for the past 18 years taping out more than 12 Asics.
Sr Manager of Strategy
Anoop Saha manages strategic growth initiatives for Siemens EDA digital design portfolio – including Catapult High-Level Synthesis and PowerPro. He also manages outbound and inbound marketing as well as demand generation. Anoop has 20 years experience in the EDA industry in various roles – from development to marketing, sales and strategy. He is currently working on system level power modeling, custom hardware accelerators and machine learning in EDA. Anoop earned his bachelor degree in Computer Science and Engineering from IIT Kanpur, India and is currently pursuing his Executive MBA from The Wharton School.
Low Power Technologist
Mahmud joined Siemens EDA’s PowerPro team in September 2021 and has been working in PowerPro’s power estimation areas. Before joining Siemens, Mahmud spent 23 years at Synopsys where he held many management and technical leadership roles in various sign-off products. He has a BSEE degree from Utah State University, MSEE and MBA degrees from San Jose State University.
Mohammed Fahad works with Siemens EDA as Technical Marketing Engineer. Fahad has more than 17 years of work experience in the field of Low Power, CDC and FPGA based system design. At Siemens EDA, Fahad is responsible for Low Power technology deployment and proliferation activities across a variety of Semiconductor customer base.
Principal Product Manager for PowerPro
Qazi is the Principal Product Manager for PowerPro low-power platform at Siemens EDA. He has over 17 years of experience spanning across ASIC/FPGA design and EDA.