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Improving Design Power and Performance with RTL Architect

January 18, 2022 @ 10:00 am - 11:00 am PST

Exploring the impact of RTL on implementation PPA has traditionally been very difficult since it was hard to connect the results to the source code.  The first difficulty occurs during elaboration and synthesis. The RTL is converted to gates and the references to the source code are lost.  The second difficulty is the gate-centric, implementation, PPA reports. The reports are designed to identify place and route issues on gate-level timing paths which is not useful to identify opportunities to improve RTL. In this webinar, Synopsys will demonstrate how to use RTL Architect™ to analyze power and restructure RTL.

Attend this Synopsys webinar to learn how to:

  • Analyze RTL to identify the largest contributions to power dissipation
  • Perform advanced glitch analysis using the hybrid PrimePower flow
  • Perform RTL restructuring tasks: group, ungroup and reparent


Listed below are the industry leaders scheduled to speak.

Jeffrey Lee

Applications Engineer, Senior Staff

Jeffrey Lee is a Product Engineer part of the New Product Introduction team. He is currently working on deploying RTL Architect to a broader customer base. His experience includes working on Design Compiler® NXT and Power Compiler™.


Vinkesh Prajapati

Applications Engineer, Senior Manager

Vinkesh Prajapati has over 15 years of experience in product and applications engineering focussing on RTL2GDSII solutions.

He is currently managing the product engineering teams for RTL Architect and Design Planning solutions based out of Bangalore, India.


Jim SchultzJim Schultz

Product Marketing Manager

Jim Schultz is the product marketing manager for RTL Architect. He has a rich background that includes both chip design and product engineering in processor, network and security markets.


January 18, 2022
10:00 am - 11:00 am PST
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