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SiFive Maximizes Compute Density With Its RISC-V Processor Cores

May 31, 2023 @ 8:00 am - 9:00 am PDT

Ansys, May 31, 2023

IP vendor SiFive has been at the forefront of RISC-V’s rapidly growing adoption across a wide array of markets and applications. In this joint presentation with Ansys, SiFive will describe how achieving maximum compute density – compute horsepower per mm2 and per mW (e.g SPECint2006/mm2) – has been a driving goal for SiFive’s portfolio of RISC-V processor cores. One of the keys to delivering high-performance in a tight area is to carefully manage dynamic power at all stages; from early RTL analysis and optimization using realistic activity, all the way to pushing the limits on efficient power distribution networks that satisfy all voltage drop requirements. SiFive and Ansys will describe design flows to meet these objectives.

Phil Dworsky, a veteran of more than 35 years in EDA and IP, heads SiFive’s worldwide strategic alliances. Prior to SiFive, Phil led Synopsys’ strategic alliances and was publisher of Synopsys Press, an imprint of Synopsys that he founded to create and deliver technical and business publications. Phil held management positions in marketing, technical marketing, and corporate applications at Synopsys, including director, marketing and applications for DesignWare IP. Phil was a co-founder and principal engineer at Performance Processors, a parallel processing company, and was also a co-founder of Silicon Solutions/Zycad, an early provider of simulation acceleration technology. He started his career at Hewlett-Packard as a hardware and software designer in the Personal Office Computer Division. Phil holds a Bachelor of Science degree with high honors in electrical engineering and computer science (EECS) from Princeton University.

Marc Swinnen is Product Marketing Director for semiconductor products at Ansys in San Jose, CA. Before joining Ansys, Marc was Director of Product Marketing at Cadence Design Systems and has worked in Marketing and Technical Support positions at Synopsys, Azuro, and Sequence Design, where he gained experience with a wide array of digital and analog design tools. Marc holds a Master’s in Electrical Engineering and a Master’s in Industrial Management from KU Leuven, Belgium and an MBA from San Jose State University, California.

By registering or attending, your personal data will be provided to ANSYS, Inc. (a United States company), and representatives may contact you. Privacy Notice. Ansys is not affiliated with the host entity.


May 31, 2023
8:00 am - 9:00 am PDT
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