Verification Futures Conference 2024 Austin

The Verification Futures conference provides a unique blend of conference presentations, exhibitions, training and industry networking sessions dedicated to discussing the challenges faced in hardware and software verification. Verification Futures provides a unique opportunity for end-users to define their current and future verification challenges and collaborate with the vendors to create solutions. It also provides an excellent opportunity to network and catch up with other verification engineers and vendors from across Europe. Finally, we welcome students to encourage them on their first step into semiconductors as verification engineers.

We have the first speaker details on CPU User Presentations

Accelerating RISC-V testbench development with open source RISC-V RTL and emulation
– Varun Koyyalagunta, Design Verification Engineer, Tenstorrent
Today’s shorter product time to market makes silicon verification runway shorter. Tenstorrent is working on CPUs based on RISC-V architecture for many AI applications. Since this is an emerging processor environment having RTL ready is not an easy task. Once RTL is available the testbench should be ready for both simulation and emulation workloads. Also, we should have all test collaterals ready to go, which involves firmware, drivers, applications etc.

At Tenstorrent we solved this problem by adopting RTL from RISC-V open source. This enabled us to shift left the emulation and simulation testbench creation. We use a standard memory interface, AXI, standard instruction interface, RISC-V Formal Interface (RVFI), and the open source CVA-6 RISC-V cpu to develop testbench architecture and collateral in advance with full architectural instruction-by- instruction checking. This helped us complete the testbench development and test infrastructure ready without our custom CPU RTL. When the inhouse RTL is ready, we could be able to replace our custom CPU RTL with open source CVA-6 processor.

This methodology helped us significantly shift left the testbench and test infrastructure readiness. Due to this, we could able to innovate in the area of test collateral creation, making emulation ready infrastructure and were confident to run application level tests the minute RTL was available. We used ZeBu for emulation work on this accelerated testbench creation with open source RTL.

3 Key Points 

·       Tenstorrent seeks to develop a high performance RISC-V core and bring it market ASAP

·       Emulation is a must for software development and function verification

·       How do we keep DV out of the critical path?