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Removing the Risk from RISC-V using the RISC-V Trace Standard
With the growing maturity of the RISC-V ISA, chip companies now have a wealth of options for implementing RISC-V cores in their latest product. At the same time the support… Read More »Removing the Risk from RISC-V using the RISC-V Trace Standard
Learn How SilTerra Uses Cello and Viola for Standard Cells and I/O Library Optimization and Characterization
As an active semiconductor foundry, SilTerra requires frequent process and technology development and enhancements, which can result in an increased need for resources and longer time to market. To meet… Read More »Learn How SilTerra Uses Cello and Viola for Standard Cells and I/O Library Optimization and Characterization