Forum
TSMC 2023 North America OIP Ecosystem Forum
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesLearn About: Emerging advanced node design challenges and corresponding design flows and methodologies for N2, N3/N3E/N3P/N3AE, N4/N4P, N5/N5A, N6/N6e/N6RF/N7, N12e, and N22 Latest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes, InFO, CoWoS®, and SoIC, 3DFabric Alliance, and 3Dblox™ standard, plus innovative 3Dblox-based design enablement technologies and solutions, targeting HPC, AI/ML, and mobile… Read More »TSMC 2023 North America OIP Ecosystem Forum
TSMC 2023 Europe OIP Ecosystem Forum
Hilton Amsterdam Airport Schiphol Schiphol Boulevard 701 Amsterdam, Amsterdam, NetherlandsLearn About: Emerging advanced node design challenges and corresponding design flows and methodologies for N2, N3/N3E/N3P/N3AE, N4/N4P, N5/N5A, N6/N6e/N6RF/N7, N12e, and N22 Latest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes, InFO, CoWoS®, and SoIC, 3DFabric Alliance, and 3Dblox™ standard, plus innovative 3Dblox-based design enablement technologies and solutions, targeting HPC, AI/ML, and mobile… Read More »TSMC 2023 Europe OIP Ecosystem Forum
Samsung Foundry Forum 2023 EMEA
Sofitel Munich Bayerpost Bayerstrasse 12, Munich, GermanyWe're inviting global partners and customers to our upcoming Samsung Foundry Forum (SFF) and Samsung Advanced Foundry Ecosystem (SAFE™) Forum 2023. The events will provide opportunities to share insights and innovative technologies to build a strong foundry ecosystem to accelerate innovation beyond boundaries. Join us to experience the spirit and power of innovation. SFF &… Read More »Samsung Foundry Forum 2023 EMEA
RISC-V in Space
Omni Interlocken Hotel 5000 Interlocken boulevard, Broomfield, CO, United StatesJoin us for "RISC-V in... Space" on November 2, 2023, as we explore the exciting intersection of RISC-V, electronics design, and space! Agenda 9:30 AM - 10:00 AM Registration & Welcome 10:00 AM - 12:00 PM Case Study Presentations: Tenstorrent, Synopsys, RISC AI, Arteris IP 12:00 PM - 1:00 PM Lunch Buffet 1:00 PM - 3:00 PM Case Study Presentations: Breker Systems, Imperas,… Read More »RISC-V in Space
TSMC 2023 Taiwan OIP Ecosystem Forum
Ambassador Hotel Hsinchu 0F, No.188, Sec. 2, Zhonghua Rd., Hsinchu City, TaiwanLearn About: Emerging advanced node design challenges and corresponding design flows and methodologies for N2, N3/N3E/N3P/N3AE, N4/N4P, N5/N5A, N6/N6e/N6RF/N7, N12e, and N22 Latest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes, InFO, CoWoS®, and SoIC, 3DFabric Alliance, and 3Dblox™ standard, plus innovative 3Dblox-based design enablement technologies and solutions, targeting HPC, AI/ML, and mobile… Read More »TSMC 2023 Taiwan OIP Ecosystem Forum
CHIPS Alliance – FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development
Google 237 Moffett Park Drive, Sunnyvale, CA, United StatesIP share and reuse is fundamental for efficient chip design. But in order to do this efficiently we need tools and methods. On the software side, the concept of package managers is widely used to build a product from many different sources, but chip designers often rely on ad-hoc solutions which tends to build up… Read More »CHIPS Alliance – FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development
CadenceCONNECT: The Race Is On!
Cadence San Jose, CA, United StatesEvent Overview Date: Monday, November 13, 2023 Time: 8:30am – 4:00pm, followed by an exclusive networking event Location: Cadence Headquarters, San Jose, CA There is an unprecedented demand for advanced-node chip design that pushes beyond traditional boundaries. Computing power, security, reliability, and other multifaceted requirements have surpassed the basic performance, power consumption, and area constraints of traditional chip design.… Read More »CadenceCONNECT: The Race Is On!
TSMC 2023 Open Innovation Platform Ecosystem Forum – China
Shangri-La Nanjing Hotel 29 Zhongyang Road, Gulou District, Nanjing, ChinaJoin us at the TSMC 2023 China OIP Ecosystem Forum! China OIP Ecosystem Forum (In-Person Event) Date: November 15, 2023 (Wednesday) Time: 9:30a.m. - 5:45p.m. Venue: Shangri-La Nanjing Hotel 329 Zhongyang Road, Gulou District, Nanjing, Jiangsu Province, 210037 China China OIP Ecosystem Forum (Online VOD Event) Date: November 22, 2023 (Wednesday) Website link to be provided in November.… Read More »TSMC 2023 Open Innovation Platform Ecosystem Forum – China
FPGA Frontrunner Meet & Greet
Thales 350 Longwater Avenue, Reading, United KingdomThe FPGA Front Runners event will be hosted by Thales at their venue in Reading. The event will focus on “Security at System Level, and what security features we need in our FPGA to support this”. If you are interested in speaking at this event please email mike.bartley@techworks.org.uk Topics for talks: What is Security in FPGA-based… Read More »FPGA Frontrunner Meet & Greet
FPGA Forum 2024 – Norway
Royal Garden Trondheim, NorwayFPGA-forum is a yearly event for the Norwegian FPGA community. FPGA-designers, project managers, technical managers, researchers, final year students and the major vendors gather for a two-day focus on FPGA. There will be presentations from the Norwegian industry about methodology and practical experience, – the universities will present new and exciting projects, and the vendors… Read More »FPGA Forum 2024 – Norway
Synopsys Technical Forum 2024
San Jose Marriott 301 S Market Street, San Jose, CA, United StatesPlease join us for our in-person Synopsys Technical Forum, taking place during SPIE Advanced Lithography + Patterning 2024. Attendees will learn about the latest industry trends along with Synopsys Manufacturing's mask synthesis, mask data prep, and lithography simulation solutions. The Tech Forum is peer-to-peer, giving you the opportunity to hear how your lithography colleagues have… Read More »Synopsys Technical Forum 2024
Agile Analog Technology Showcase Event
The Royal Society of Edinburgh 22-26 George Street, Edinburgh, United KingdomLearn how innovative analog IP can help analog design engineers. Agile Analog is transforming the analog IP industry, with Composa, our configurable, multi-process technology that automatically generates analog IP. We offer a wide-variety of novel analog IP solutions for Data Conversion, Power Management, IC Monitoring, Security and Always-On IPs. Applications include High Performance Computing (HPC),… Read More »Agile Analog Technology Showcase Event