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Synopsys Virtual Prototyping Day 2024
July 11, 2024 @ 9:15 am - 12:00 pm PDT
Join us at Virtual Prototyping Day 2024 to hear about the latest deployed virtual prototyping innovations. This event highlights applications from around the world using the latest virtual prototyping technology, covering applications from automotive, AI, and data center domains.
Industry leaders will share their experiences with the latest techniques and methodologies using virtual prototypes for early software development and architecture exploration. Presentations will highlight how virtual prototypes help to address the increased architectural challenges of highly complex SoC and multi-die architecture designs, as well as enabling early embedded software development, debug, and testing.
Welcome
9:15 AM-9:30 AM
General Session
Join Marc Serughetti as he welcomes you to Virtual Prototyping Day.
M S
Marc Serughetti
VP Product Management
Synopsys
Leveraging Virtual Platforms to Shift-left HW/SW Verification
July 11, 2024
9:30 AM-9:55 AMPT
Software Development & Test
As SoC(System-On-Chip) complexity continues to increase due to the hardware-dependent software functionality, hardware/software co-verification should be done in the early design stage. This presentation shows how the virtual platform technology enables early software development as well as the concurrent hardware/software co-verification for SSD(Solid State Drive) development as an industrial case study
Kyungsu Kang
Samsung
Pre-Design Verification and Optimization for On-chip Interconnects
July 11, 2024
9:30 AM-10:00 AMPT
System Architecture Design & Exploration
Data movement plays a big role in overall SoC performance. It is essential to qualify the on-chip interconnect architecture as early as possible – to verify algorithms applied on the on-chip interconnect, determine the best performance tuning settings in the design, and assist in power and performance projections – all before RTL is available.
This presentation discusses the collaboration between Microsoft and Synopsys on the on-chip interconnect model development and exploration using Platform Architect, the many learnings that were made along the way, and the achievements made by the team.
Charlie Zhou
Microsoft
Monica Tang
Microsoft
Application-level Hybrid Emulation for Software-Defined-Systems
July 11, 2024
9:55 AM-10:25 AMPT
Software Development & Test
Over the last 10 years, Hybrid Emulation has been widely deployed for Early SW bring-up and HW/SW validation. Combining a fast virtual prototype of the CPU sub-system with the RTL of the remaining SoC running on an emulator typically produces a 10x speed-up over full emulation setups and saves precious emulator resources.
Recent advances in both virtual prototyping and emulation now yield another leap in hybrid performance, which enables pre-silicon execution of full Software stacks, including end-user applications. In an emerging world of Software-defined Systems, this provides invaluable insight for the validation and optimization of HW resources and their deployment by Software applications under realistic use-case scenarios, like AI-enabled functions, autonomous drive stacks, end-to-end networking applications, etc.
In this tutorial, we will first review the latest state-of-the-art of hybrid emulation technologies and use-cases. We will then illustrate the application of hybrid emulation for the pre-silicon validation and optimization of Software-defined Systems.
Tim Kogel
Sr. Director for Technical Product Management
Synopsys
Network-on-Chip Design for Automotive Processor and Platform Integration for Front-end Benchmarking
July 11, 2024
10:00 AM-10:30 AMPT
System Architecture Design & Exploration
In this presentation we would like to address our flow of architectural exploration of StellarApp SoC using Synopsys Platform Architect tool and Designware LPDDR5 model. Validation of automotive SoCs using valid benchmark is must to guarantee all performance and design parameters are met and this could not be possible without usage of Synopsys Platform Architect tool: 1) to assemble models with different level of abstraction and from 3rd parities (ARM and Arteris ), 2) easy configuration and sweeping their parameters in different round of fast simulation, 3) effective analysis from both HW and SW point of view and 4) finally accurate model of Synopsys DW_LPDDR5 which helped us extremely fast and effective to validate our SoC with different benchmark.
Filippo Colaninno
ST
Virtual Prototypes Drive RISC-V Software Development, Optimization and Test
July 11, 2024
10:25 AM-10:55 PMPT
Software Development & Test
As RISC-V processors gain momentum in the semiconductor market, attention is shifting from a complete focus on the processor design to a shared focus on processor and software. Just as with other processor architectures, software development is most often the critical path to SoC projects. Challenges for software development include how to shift left software development, how to optimize architecture, effective debug, software optimization, and continuous integration and DevOps flow integration.
Virtual prototypes provide a productive answer to these challenges. Virtual prototypes, with ImperasFPM RISC-V fast processor models and the Virtualizer tools, enable pre-silicon software development. The virtual prototypes also enable architecture optimization (RISC-V custom instructions) and software optimization with Virtualizer analysis tools. Virtualizer also supports hardware-software debug, and is used every day in DevOps flows.
With the ImperasFPMs supporting RISC-V processor IP from both vendors and custom processors, users have full flexibility to design in a RISC-V domain-specific processor, and build the software to execute on their SoC platform.
Larry Lapides
Exec. Director, Business Development
Synopsys
Early Performance Exploration of Kalray ManyCore IC Using App Dataflows w/Arm Performance Models
July 11, 2024
10:30 AM-11:00 AMPT
System Architecture Design & Exploration
Early validation of system architecture decisions is crucial to avoid delays and meet product requirements. Kalray’s ManyCore chips, designed for storage, compute and AI applications, need high compute efficiency and optimized dataflows between the chip’s interfaces, main memory, and local memory. The efficiency of these dataflows depends on various hardware and software parameters, such as workload patterns, the number of concurrent workloads, DRAM transaction distribution, DRAM scheduling policies, and interconnect configurations.
Using Synopsys Platform Architect, with generic IP and Arm performance models, we created a performance SystemC simulation platform that helps validate architectural assumptions early on, guiding data-driven decisions during chip design. Our simulation platform, which can be quickly developed without needing RTL availability, supports continuous integration to detect potential architecture regressions. We plan to enhance the model’s accuracy by integrating IP models as the design progresses.
Pierre-Yves Taloud
Kalray
Enflame Virtual Prototyping for AI Chip Early SW Development
July 11, 2024
10:55 AM-11:25 AMPT
Software Development & Test
Enflame is an AI chip start-up company. It also develops runtime/framework SW to run AI models on its chip. Synopsys Virtualizer helps to shift-left SW development by 6 months. On virtual prototyping of the whole AI chip, HW designer got early feedback for new architecture; Performance optimization started before chip tap-out; Hybrid virtual prototyping even help to verify RTL design. HW and its SW’s time-to-market was reduced. This session will present:
Why Virtual Prototyping
Virtual Prototyping Development
Usage Model
Achievements and Next Steps
Gang Jia
Enflame
Use of Platform Architect for Architecting the Next Generation AURIX Microcontroller
July 11, 2024
11:00 AM-11:30 PMPT
System Architecture Design & Exploration
Virtual prototyping is key for early design space exploration and proper architecture definition for any given SoC platform. This talk focuses on how the Synopsys Platform Architect tool is used to help architect the next generation AURIX microcontroller:
Primarily, the tool is used to execute system performance simulations for different architectural domains such as compute, interconnect and memory.
Our simulation platform comprises of several components with different modelling abstraction levels, such as Synopsys library models, custom developed models and even RTL models.
Simulations are executed using both standard code benchmarks and synthetic traffic as stimuli.
The simulation results are analysed using standard metrics such as latency, bandwidth, etc., with deeper analysis using automated custom post-processing scripts
Sandeep Vangipuram
Infineon Technologies
Orchestrating SoC Design Space Exploration to Optimize Performance for Multi-Agent Core-IO Workloads
July 11, 2024
11:30 AM-12:00 PMPT
System Architecture Design & Exploration
Optimizing the performance of System-on-Chip (SoC) designs requires a comprehensive understanding of the workload characteristics and complex interactions between fabric interconnects, system caches, and DRAM controllers. In this presentation we will share a robust methodology to model different workloads and orchestrate design space exploration (DSE) for performance optimization of these critical SoC components using Synopsys Platform Architect.
Our approach utilizes the advanced capabilities of Synopsys Platform Architect to create detailed and accurate workload models and use performance models of the fabric, system cache, and DRAM controller. By integrating these models with heuristic optimization techniques, we conduct an efficient and exhaustive exploration of the design space, identifying configurations that offer the best trade-offs between performance, power, and area (PPA). We specifically address the challenges posed by multi-agent Core-IO traffic, focusing on the intricate interactions between compute and memory subsystems.
The results demonstrate marked improvements in design efficiency, with optimized configurations achieving orders of improvement in Performance compared to baseline designs. This methodology equips industry practitioners with a powerful toolset for early-stage SoC DSE, enabling more informed design decisions and enhancing the overall performance of computing systems.
Melwyn Scudder
Intel NEX