IP
HiPEAC
Pierre Baudis Convention Centre 11 esplanade Compans Caffarelli, Toulouse, FranceThe HiPEAC conference is the premier European forum for experts in computer architecture, programming models, compilers and operating systems for general-purpose, embedded and cyber-physical systems. Areas of focus and integration include safety-critical dependencies, cybersecurity, energy efficiency and machine learning. The HiPEAC 2023 conference will take place in Toulouse, France. Associated workshops, tutorials, special sessions, several… Read More »HiPEAC
ASP-DAC 2023
Tokyo Odaiba Miraikan 2 Chome-3-6 Aomi, Tokyo, Koto CIty, JapanASP-DAC is the largest conference in Asia and South-Pacific regions on Electronic Design Automation (EDA) area for VLSI and systems. ASP-DAC has been started at 1995 and this ASP-DAC 2023 is 28th conference. ASP-DAC 2023 offers you an ideal opportunity to touch the recent technologies and the future directions on the LSI design and design… Read More »ASP-DAC 2023
Making Way for Open-Source Hardware
This is a thought leadership piece that highlights the significance of open-source hardware. Tony McDowell (Rapid Silicon) and Adam Taylor (Adiuvo) will discuss the innovations and changes required to bring awareness to open-source. Rapid Silicon's Raptor Design Suite toolchain has already proven that designs can be secure even in an open-source environment. Rapid Silicon The… Read More »Making Way for Open-Source Hardware
Webinar: The Rise of the Chiplet
Join us this Thursday, February 9th to talk about The Rise of the Chiplet. Moderated by SemiEngineering’s Brian Bailey, this webinar will dive into the current landscape for chiplet technology, predictions for the coming years, what’s needed for chiplet adoption, and the status and evolution of die-to-die interface standards. Achronix’s Nick Ilyadis, Semico’s Rich Wawrzyniak, and ODSA’s Bapi… Read More »Webinar: The Rise of the Chiplet
SemIsrael Tech Webinar
13:30 - 14:00 Low Power Design An Effective Path to Low-Power Design The demand for green and energy efficient products is increasing but getting there has never been easy. In this session, we will look at how to design low-power, IPs/SOCs by including low-power techniques in your design flows and tracking power throughout the RTL… Read More »SemIsrael Tech Webinar
Removing the Risk from RISC-V using the RISC-V Trace Standard
With the growing maturity of the RISC-V ISA, chip companies now have a wealth of options for implementing RISC-V cores in their latest product. At the same time the support ecosystem is growing, with standards now defined for support technologies such as processor trace, which gives developers access to critical insights and forensic capabilities to… Read More »Removing the Risk from RISC-V using the RISC-V Trace Standard
Learn How SilTerra Uses Cello and Viola for Standard Cells and I/O Library Optimization and Characterization
As an active semiconductor foundry, SilTerra requires frequent process and technology development and enhancements, which can result in an increased need for resources and longer time to market. To meet this ongoing challenge, high productivity library optimization and validation are required. In this webinar, we will share the challenges of developing, optimizing, and validating different… Read More »Learn How SilTerra Uses Cello and Viola for Standard Cells and I/O Library Optimization and Characterization
ISSCC 2023
Marriott Marquis 780 Mission Street, San Francisco, CA, United StatesISSCC 2023 is planned as a fully in-person event. On-demand access to ISSCC papers and educational material will be possible for people who cannot travel to San Francisco, but the conference will be optimized for an in-person experience. We keep monitoring the COVID-19 pandemic and we will promptly inform you should any change in our… Read More »ISSCC 2023
Introduction to UCIe
UCIe™ — Universal Chiplet Interconnect Express™ — is an open industry standard founded by the leaders in semiconductors, packaging, IP suppliers, foundries, and cloud service providers to address customer requests for more customizable package-level integration. The newly formed UCIe Consortium fosters an open chiplet ecosystem by offering high-bandwidth, low-latency, power-efficient, and cost-effective on-package connectivity between… Read More »Introduction to UCIe
RISC-V Webinar from Andes
Andes Technology is going to host a webinar at 17:00 PM on February 22 (Japan Standard Time (JST) and Korea Standard Time (KST)). Andes speakers will present Andes comprehensive hardware and software solutions. Samuel Chiang, Deputy Technical Director of Marketing, will present a wide range of applications which have adopted RISC-V solutions and will introduce… Read More »RISC-V Webinar from Andes
Phil Kaufman Award & Banquet
The GlassHouse 2 S Market Street, San Jose, CA, United StatesThe Phil Kaufman Award honors individuals who have had a demonstrable impact on the field of electronic system design through technology innovations, education/mentoring, or business or industry leadership. The award was established as a tribute to Phil Kaufman, the late industry pioneer who turned innovative technologies into commercial businesses that have benefited electronic designers. Time 6:30… Read More »Phil Kaufman Award & Banquet
Hardware Security 2.0: What Are The New Frontiers?
The CAD for Trust and Assurance website is an academic dissemination effort by researchers in the field of hardware security. The goal is to assemble information on all CAD for trust/assurance activities in academia and industry in one place and share them with the broader community of researchers and practitioners in a timely manner, with… Read More »Hardware Security 2.0: What Are The New Frontiers?