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SemIsrael Tech Webinar
February 14 @ 1:30 pm - 5:00 pm IST
13:30 – 14:00 Low Power Design
An Effective Path to Low-Power Design
The demand for green and energy efficient products is increasing but getting there has never been easy. In this session, we will look at how to design low-power, IPs/SOCs by including low-power techniques in your design flows and tracking power throughout the RTL development cycle to realize energy efficient designs. PowerPro’s low-power design methodology has been effectively used by Arm, Samsung, Cisco, and many others.
Principal Product Manager for PowerPro
Qazi is the Principal Product Manager for PowerPro low-power platform at Siemens EDA. He has over 17 years of experience spanning across ASIC/FPGA design and EDA.
14:00 – 14:30 Advanced Process Nodes
Journey to the Best Performance-per-Watt at 3nm and Below
In this session, Synopsys will discuss the journey to achieving best design results at 3nm and below technology nodes, especially designs utilizing the unique Hybrid-row placement, and how innovative AI-driven design methodologies, that can shift-left downstream physical effects and signoff requirements, are necessary to unlock the full performance-per-watt potential the latest advanced process nodes.
James Chuang is a Product Manager at Synopsys. He has worked in the EDA industry for more than 15 years, with experience in Digital Implementation and Signoff solutions. He is currently responsible for Product Management for Fusion Compiler and DSO.ai at Synopsys.
14:30 – 15:00 Formal Verification
How Much Formal Verification is Enough? A Verification Method For High-Consequence Systems
In hardware verification world there is a question that is being asked always – how much verification is enough? It applies to all verification techniques. Several techniques developed means to measure it with functional and code coverage and it does apply to formal verification without reserves.
The question we tackle with current talk is: how much formal verification is enough?
One would suggest a flow that should answer the question, starting with requirements specification, planning, testbench development, prove properties, coverage measure and sign-off. This approach has its pitfalls like missing requirements leading to missing properties, verification pitfalls: over and under constraining, mistakes in assertion writing, all leading to a negative outcome of verification: re-design and re-verification.
With current presentation we will walk you through an automated and formal check on the properties to check for completeness where all possible input sequences are examined, all outputs are verified at all times. The complete property set forms an abstract model of the system where all design behavior is exposed and can back-out undocumented specification from the abstract model building a closed-loop verification process using SystemVerilog Assertions.
The GapFree verification method is ideal for high-consequence systems where the complete verification is required and is unique among formal property verification tool capabilities.
Formal Verification Solutions Product Manager
Nicolae Tusinschi is a product manager for formal verification solutions at Siemens EDA. He holds a Master’s degree combined between the University of Southampton and the University of Kaiserslautern. After a Master’s thesis at Continental, Nicolae joined OneSpin, where he worked in QA, then as a product specialist and later served as product owner for design verification tools at OneSpin. His key projects include integrating simulation coverage with formal metrics, leveraging coverage results in the verification process, formal verification of RISC-V cores.
15:00 – 15:30 High-Level Synthesis
High-Level Synthesis – Are You Still Missing Out?
In this session we will look at how C++ and SystemC High-Level Synthesis is more than just converting C++/SystemC to RTL. We’ll cover language choice, architecture exploration, power estimation and optimization that all work to deliver competitive RTL in a faster time with lower cost. Customers who have spoken publicly about Catapult HLS usage include NVIDIA, Facebook, Google, Qualcomm, ST, Bosch, NXP, NASA JPL, and many more. You won’t be first, but you don’t have to be last.
Technical Product Management Director
Stuart is responsible for Catapult HLS Synthesis and Verification Solutions since July 2017. Prior to this new role, Stuart had been successfully managing the North American FAE team for Mentor/Siemens and Calypto Design Systems and was key to the growth achieved for the CSD products after the Calypto acquisition. Moving from the UK in 2001 to work at Mentor Graphics, Stuart held the position of Technical Marketing Engineer, initially on the Precision RTL synthesis product for 6 years and later on Catapult for 5 years. He has held various engineering and application engineering roles ASIC and FPGA RTL hardware design and verification. Stuart graduated from Brunel University, London, with a Bachelors of Science.
15:30 – 16:00 Physical Planning and Timing Closure
Excellicon Product Portfolio
Physical Planning and Timing Closure. Excellicon focus is on helping designer from early stages to ensure timing requirements are properly developed and verified prior to handoff to physical design implementation. Product portfolio is designed to ensure quickest and most efficient path to timing closure and reducing unnecessary iterations.
Over 20 years of chip design experience, designing complex SOCs in networking, communications, imaging, among others. Himanshu’s background and experience involving SOC realization resulted in publication of his book; “Advanced ASIC Chip Synthesis: Using Synopsys Design Complier and Primetime” as a practical guide to synthesis and static timing analysis. Prior to Excellicon, Himanshu served as an advisory board member of several EDA companies. His experience is crucial to ensuring development of tools fit for everyday design by front and back-end engineers and shaping the future direction of Excellicon.
16:00 – 16:30 Custom Silicon
Accelerating Data For a Connected World: The Power of Optimized Silicon
In this webinar we will explore the ways in which purpose-built silicon IP and system-on-a-chip (SoC) solutions are of paramount importance to the development of faster and more power efficient data networks, as well as the growth of cloud computing and other emerging applications. We will also discuss the challenges and opportunities associated with the adoption of these solutions and provide insights into how SoCs with application-optimized chiplets in highly advanced multi-die packages are the wave of the future for accelerating data connectivity in the digital infrastructure world.
SVP Corporate Marketing
Sudhir Mallya is Senior Vice President of Corporate Marketing at Alphawave IP. He is based in Silicon Valley and has over 25 years of experience at leading global semiconductor companies with executive positions in engineering, marketing, and business unit management. His experience spans custom silicon (ASICs) and application-specific (ASSPs) products across multiple application domains including data centers, networking, storage, and edge-computing. He has an MSEE from the University of Cincinnati and a bachelor’s in electrical engineering from the Indian Institute of Technology, Bombay.
16:30 – 17:00 RISC-V Verification & Software Development
RISC-V Models For Verification, Architectural Exploration, and Software Development
The design freedoms of RISC-V offer systems and SoC developers new flexibility to optimize a processor for the requirements of the target application. Now Architectural Exploration is not just about the configuration of multi-core designs, but the analysis of the application and potential advantages of custom instructions. Custom extension can boost the performance for a target class of operations, or support new multi-core communication methods. Software development with virtual prototypes is well established, but new to RISC-V is the advantage of these platforms offer to end users migrating legacy applications to the new RISC-V based device, well before silicon is available. For SoC teams optimizing a RISC-V processor they also need to address the additional challenge of RISC-V verification, open standards such as RVVI (RISC-V Verification Interface) are helping the ecosystem support for standards-based test benches and Verification IP. This talk highlights the RISC-V models that are unifying the hardware, software, and verification teams across all phases of RISC-V projects with dependable quality and efficiency.
Vice President Sales
Prior to joining Imperas, Larry ran sales at Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity’s IPO (the top performing IPO of 2001), and afterwards as Verisity solidified its position as the fifth largest EDA company. Before Verisity and SureFire Verification (acquired by Verisity), Larry held positions in sales and marketing for Exemplar Logic and Mentor Graphics. Larry was recently an Entrepreneur-in-Residence at Clark University’s Graduate School of Management, where he developed and taught a course on Entrepreneurial Communication and Influence. Larry holds an MBA from Clark University in addition to his MS Applied & Engineering Physics from Cornell University and BA Physics from the University of California Berkeley.