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Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect… Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
Multi-die SoC containing multiple RISC-V clusters, GPU, NPU, accelerators and DNN have considerable benefits for applications in automotive, space and industrial. Architecture exploration of the chiplet-based SoC requires multiple interconnect… Optimizing Chiplet architectures of RISC-V clusters, GPU and DNN using System-Level IP
CadenceLIVE Silicon Valley 2024
Santa Clara Convention Center 5001 Great America Parkway, Santa ClaraJoin us for CadenceLIVE Silicon Valley 2024 on April 17 at the Santa Clara Convention Center. This annual user conference features peer presentations that offer solutions for today’s design challenges… CadenceLIVE Silicon Valley 2024