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From code to solution: tools and tactics for aerospace fault code troubleshooting

Join us in this insightful webinar as we delve into the world of aerospace and defense electrical fault code troubleshooting, unveiling the power of Capital™ Service Explorer. Discover innovative strategies to diagnose issues swiftly, minimizing downtime and optimizing product performance. Explore real-world examples showcasing how Capital Service Explorer facilitates the identification of commonalities among multiple… Read More »From code to solution: tools and tactics for aerospace fault code troubleshooting

Navigating the Power Challenges of Datacenter Infrastructure

The surge in applications such as AI, HPC, and GPU-intensive workloads requires unparalleled performance, placing cloud vendors and enterprise datacenters under immense pressure to simultaneously maximize power efficiency, reduce costs, and adhere to stringent environmental standards. Join us for a 1-hour panel discussion featuring unique perspectives from industry experts at Intel, Microsoft, Arm and proteanTecs. We will explore… Read More »Navigating the Power Challenges of Datacenter Infrastructure

Efficient Design Methodology for 112G Interface Compliance

As 112G+ data transfer becomes the new normal, companies risk schedule delays unless they improve the efficiency of their multi-board design methodology. An efficient design methodology looks at signal and power integrity early and often as the design progresses. In addition, with the precision required to meet 112G compliance, companies can take extra steps to… Read More »Efficient Design Methodology for 112G Interface Compliance

What’s New About Virtuoso Layout Suite?

Accelerate Layout Creation with Automated Place and Route in Virtuoso Studio How can you cut down custom layout implementation from days to minutes? Custom device-level automated place and route (APR) for advanced nodes has very different requirements than mature node chip assembly routing. With our new unified APR flow-based user interface integrating the various automation… Read More »What’s New About Virtuoso Layout Suite?

New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

Designers increasingly use complex reset signaling architectures to meet high-performance, low-latency, and low-power requirements. Specifically, independent reset domains are created by complex reset sequences, reset circuitry, and the intermixing of IPs with different reset schemas, power-management domains, and security domains or functionality. This increase in reset signaling complexity is creating new RDC verification challenges that… Read More »New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

Virtuoso – Save on Signoff Effort with In-Design DRC and Fill

Virtuoso Layout Suite has pioneered in-design DRC checking and fixing in the layout editor. However, many of you have realized that the lack of completeness of rules in the techfile has caused many violations to fall through the cracks and are discovered later during signoff. An in-design DRC checking with signoff rule decks often comes… Read More »Virtuoso – Save on Signoff Effort with In-Design DRC and Fill

Shift-Left Thermal Analysis with AI-Enabled Celsius Studio Platform

With the growing complexities of 3D-ICs, chiplets, advanced packaging, and high-performance boards, engineers need a unified solution that provides early insight and analysis to detect and correct design problems before it is too late. This solution must also offer the ability to simulate the entire design efficiently, providing confidence in system signoff. Join our webinar… Read More »Shift-Left Thermal Analysis with AI-Enabled Celsius Studio Platform

High-Performance RTL Simulation Workflow with Vivado and Active-HDL

Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility, acceleration capability, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs).… Read More »High-Performance RTL Simulation Workflow with Vivado and Active-HDL

Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification

Gate-level simulations (GLS) are a crucial step in the verification of an ASIC/FPGA. GLS is used for verifying power-up, reset operation, timing, multi-cycle paths, and power estimation. However, GLS can be a bottleneck in the project cycle due to its complexity. The nature of a GLS can cause simulations to run much longer than the… Read More »Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification

Analyze the Impact of Surface Defect Dot on Short Circuit Phenomena in SiC Devices

Learn How STMicroelectronics Silicon Carbide (SiC) Research Team uses Silvaco TCAD to Analyze the Impact of Surface Defect Dot on Short Circuit Phenomena in SiC Devices During SiC device switching operations, it is possible that devices could be reaching abnormal overload conditions, which is why some applications require “robustness” specifications (e.g., Short Circuit and UIS… Read More »Analyze the Impact of Surface Defect Dot on Short Circuit Phenomena in SiC Devices

High-Performance RTL Simulation Workflow with Quartus and Active-HDL

Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility, acceleration capability, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs).… Read More »High-Performance RTL Simulation Workflow with Quartus and Active-HDL