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Jasper User Group 2023
Ready to share and discuss the latest design and verification best practices with your peers from around the world? It’s time for our annual CadenceCONNECT: Jasper™ User Group Conference, held on October 18 and 19 at the Cadence San Jose campus. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers from around… Jasper User Group 2023
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Soar to New Heights of Productivity using Cadence Managed Cloud Services
Date: Wednesday, October 18, 2023 Time: 8:30am PT | 10:30am CT | 11:30am ET Join us for this 45-minute webinar to learn how the Cadence-managed, EDA-optimized, ready-to-use, and secure ISO-certified cloud platform delivers a fully integrated and proven environment to jump-start product design, verification, and implementation. See the platform in action as we demo the productivity features… Soar to New Heights of Productivity using Cadence Managed Cloud Services
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The Race is On!
Brazos Hall East 4th Street, Austin, TX, United StatesEvent Overview Date: Wednesday, October 18, 2023 Time: 8:30am – 4:00pm, followed by an exclusive networking event Location: Brazos Hall, Austin, TX There is an unprecedented demand for advanced-node chip design that pushes beyond traditional boundaries. Computing power, security, reliability, and other multifaceted requirements have surpassed the basic performance, power consumption, and area constraints of traditional chip design. The… The Race is On!
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System-Level Thermal Signoff from Chips Through to Racks
Today’s modern electronic designs require ever more functionality and performance to meet consumer demand. These challenges become more critical and complex when resistive losses in PCB and package structures are significant since resistive losses are temperature dependent. In this webinar, we will look at an electrothermal co-simulation solution for the full hierarchy of electronic systems… System-Level Thermal Signoff from Chips Through to Racks
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Samsung Foundry Forum 2023 EMEA
Sofitel Munich Bayerpost Bayerstrasse 12, Munich, GermanyWe're inviting global partners and customers to our upcoming Samsung Foundry Forum (SFF) and Samsung Advanced Foundry Ecosystem (SAFE™) Forum 2023. The events will provide opportunities to share insights and innovative technologies to build a strong foundry ecosystem to accelerate innovation beyond boundaries. Join us to experience the spirit and power of innovation. SFF &… Samsung Foundry Forum 2023 EMEA
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High Reliability and Functional Safety Applications for FPGA
When designing any new system, safety and reliability are key factors in determining if a system is safe for real-world deployment and if there are sufficient contingency plans for worst case scenarios. This is no different for the designs targeted for FPGAs based deployments. Today, FPGA based designs are utilized in many safety critical systems in the… High Reliability and Functional Safety Applications for FPGA
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SemIsrael Expo 2023
Avenue Convention Center Airport City, IsraelSemIsrael Expo 2023 is the premier professional semiconductor event in Israel. The event brings together hundreds of Israeli semiconductor professionals from all fields and aspects of the semiconductor industry. The Expo will host some 750 semiconductor professionals from all the Israeli semiconductor community; local fabless & startups, local R&D offices of multinationals and IDMs, foundries,… SemIsrael Expo 2023
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Silvaco UseRs Global Event (SURGE) 2023 – USA
Silvaco UseRs Global Events (SURGE) bring together users, developers, and industry experts of the EDA, IP, and TCAD communities to understand new semiconductor technologies, innovative applications, and techniques for realizing advanced designs. Presentations A variety of presentations will cover semiconductor device simulation, circuit design and verification, and IP design. Roadmaps and exciting technology updates will… Silvaco UseRs Global Event (SURGE) 2023 – USA
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STAC Summit
The Metropolitan Club 233 South Wacker Drive, Chicago, IL, United StatesSTAC Summits bring together CTOs and other industry leaders responsible for solution architecture, infrastructure engineering, application development, machine learning/deep learning engineering, data engineering, and operational intelligence to discuss important technical challenges in trading and investment. WHEN Tuesday, October 31, 2023 STAC Exchange (Exhibits) opens at 8:30am CDT Conference starts at 9:00am CDT Networking lunch at… STAC Summit
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Enhance Verification Quality with the Xcelium Mixed-Signal App
The comprehensive verification of analog mixed-signal (AMS) designs has challenges in schedules and implementations due to the vast divergence in design flows of the analog and digital portions of the SoC. These discrepancies include priorities in simulation cycles (accuracy versus performance), design methodologies, and verification of functionality. Over multiple decades, design verification (DV) has evolved… Enhance Verification Quality with the Xcelium Mixed-Signal App
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Mastering the Art of Managing IP, Chiplets, and Design Data
Join us on Wednesday, November 1st, for an eye-opening exploration of the inadequacy of common design data and IP management capabilities in the face of today’s intricate semiconductor chip designs. Discover the keys to unlocking unparalleled success in your upcoming designs through cutting-edge capabilities and strategies that are reshaping the industry. Don’t miss this exclusive opportunity… Mastering the Art of Managing IP, Chiplets, and Design Data
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Warp Speed Gate-Level Simulations with the Xcelium Multi-Core App
Are you ready to lead the way in gate-level digital simulations (GLS)? Dive into Cadence’s exclusive webinar and uncover the revolutionary Xcelium Multi-Core (MC) App—a game changer for GLS, allowing you to parallelize and expedite simulations like never before. What You'll Gain: Insight: Understand why the Xcelium MC App is crucial for DV engineers looking… Warp Speed Gate-Level Simulations with the Xcelium Multi-Core App
12 events found.