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2024 TSMC Europe OIP Ecosystem Forum
Hilton Amsterdam Airport Schiphol Schiphol Boulevard 701 Amsterdam, Amsterdam, NetherlandsLearn About: Emerging advanced node design challenges and corresponding design flows and methodologies for A16, N2 and N3 processes Latest updates on TSMC 3DFabric™ chip stacking and advanced packaging processes, InFO, CoWoS®, and SoIC, 3DFabric Alliance, and 3Dblox™ standard, plus innovative 3Dblox-based design enablement technologies and solutions, targeting HPC, AI/ML, and mobile applications Comprehensive design… 2024 TSMC Europe OIP Ecosystem Forum
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Ansys-Synopsys Technology Update: The Latest Advances in Multi-Die Design
The semiconductor industry is rapidly adopting 2.5D and 3D multi-die designs as the significant benefits have become clear for applications like HPC, GPU, mobile, and AI/ML. Multi-die design technology has been quickly evolving with early experiences leading to the development of more advanced implementation and analysis techniques. For the past years, Synopsys and Ansys have… Ansys-Synopsys Technology Update: The Latest Advances in Multi-Die Design
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Fast Track RTL Debug with the Verisium Debug Python App Store
Working with debugging scripts locally and manually can be challenging, as can reusing and organizing them. What if there was a way to create your own app with the required functionality and to register it with the tool? The answer lies in the Verisium Debug Python App Store. Instantly add additional features and capabilities to… Fast Track RTL Debug with the Verisium Debug Python App Store
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Ansys IDEAS User Conference India 2024
Join us for the Ansys IDEAS India User Conference 2024 — a place to catch up on industry best practices and the latest Semiconductor design advances. IDEAS will explore future trends with keynotes from industry leaders and offer technical insights from expert chip designers from many of the world’s top semiconductor companies. Overview At this… Ansys IDEAS User Conference India 2024
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Tower Semiconductor – Technical Global Symposium 2024
Hyatt Regency Santa Clara 5101 Great America Parkway, Santa Clara, CA, United StatesTGS offers a wonderful opportunity for networking, learning, and sharing the latest technology developments with our community, as well as meeting with Tower’s executives and team of experts. We invite you to join us! Time Session Speaker 9:00 – 10:00 Registration 10:00 – 10:05 Opening Mr. Lei Qin, SVP of Worldwide Sales 10:05 – 10:40… Tower Semiconductor – Technical Global Symposium 2024
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Webinar 2: Tessolve AI assisted DV Flow
With the increasing importance of AI in engineering and the exciting potential for it’s use in Design Verification, Tessolve has been working on improving internal DV processes, with impressive reductions in both effort and costs, and with many clients to improve both efficiency and quality in DV through AI. In this series of 3 short… Webinar 2: Tessolve AI assisted DV Flow
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Boost your verification productivity with Questa Verification IQ
This session will explore Questa Verification IQ (VIQ), Siemens EDA’s next-generation collaborative and data-driven verification solution. VIQ revolutionizes the verification process by providing advanced analytics, enhanced collaboration, and comprehensive traceability. By leveraging machine learning, VIQ significantly enhances verification efficiency to boost your productivity. What you will learn: How to implement a collaborative, plan-driven verification process,… Boost your verification productivity with Questa Verification IQ
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Accelerating Electric Vehicle Development: Integrated design flow for power modules with functional safety and reliability focus
This webinar to delve into the integrated design flow for power modules for electric vehicles (EVs) for enhanced functional safety and reliability. The power modules are distinguished by their high voltage and current requirements, substantial power dissipation, and the resulting temperature rise. Ensuring their safety and reliability is paramount. We will explore how Cadence’s cutting-edge… Accelerating Electric Vehicle Development: Integrated design flow for power modules with functional safety and reliability focus
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FPGA Front Runner: FPGA Safety and Security
The Cass Centre Shaftesbury Road, Cambridge, United KingdomThis event covers the challenges in ensuring an FPGA is secure and demonstrably safe as per the relevant industry safety standards. This includes supply chains, FPGA hardware and the IP used on the FPGA Agenda (GMT) Time Speaker Details 09.30 Arrival and registration 10.00 Tobias Adryan, Synopsys Securing FPGAs Beyond the Bitstream 10.30 Espen Tallaksen,… FPGA Front Runner: FPGA Safety and Security
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DVClub Europe – AI/ML in Verification
This DVClub will consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to design verification. Agenda (GMT): Time Session Description Slides Videos 12.00 GMT Welcome and Introduction – Mike Bartley, Tessolve Mike Bartley,Tessolve 12.00 GMT Hardik Raina, Agnisys, Inc - Genetic Algorithms for Automated Verification from VCD Data. 12.20… DVClub Europe – AI/ML in Verification
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Webinar 3: Tessolve AI assisted advanced DV Flow and Use cases
Webinar 3: Tessolve AI assisted advanced DV Flow and Use cases With the increasing importance of AI in engineering and the exciting potential for it’s use in Design Verification, Tessolve has been working on improving internal DV processes, with impressive reductions in both effort and costs, and with many clients to improve both efficiency and quality… Webinar 3: Tessolve AI assisted advanced DV Flow and Use cases
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Keysight EDA 2025 Launch event
New EDA Tools for 5G and AI Infrastructure Design We are ready to share the latest release of our electronic design automation (EDA) software suites. This update will help you design smarter with faster multidomain insights and workflows enhanced by artificial intelligence (AI). Get the Roadmap The webinar will kick off with an overview of… Keysight EDA 2025 Launch event
12 events found.