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Ansys IDEAS User Conference India 2024
November 20 @ 9:00 am - 5:00 pm UTC+5.5
Join us for the Ansys IDEAS India User Conference 2024 — a place to catch up on industry best practices and the latest Semiconductor design advances. IDEAS will explore future trends with keynotes from industry leaders and offer technical insights from expert chip designers from many of the world’s top semiconductor companies.
Overview
At this premier conference, you will:
- Discover Key Insights: Learn from industry experts and simulation specialists about cutting-edge techniques and strategies in on-chip power integrity and reliability
- Explore Multi-Scale Multiphysics Challenges: Dive into complex topics, including multi-scale, multiphysics simulations essential for 3DICs and heterogeneous integration
- Accelerate Innovation: Gain valuable knowledge on how advanced simulation technologies like Sigma-DVD can streamline design processes and drive innovation
- Network with Experts: Connect with peers and Ansys experts, sharing experiences and exploring new opportunities for collaboration
IDEAS India is your opportunity to deepen your understanding of power-noise-reliability sign-off for Chip-Package systems, enhance your skills, and advance your engineering capabilities. Don’t miss this chance to be part of the conversation shaping the future of technology.
Key Discussion Topics
- SoC Power-Integrity and Reliability Sign-off
- Advanced Power Integrity Flows: Sigma-DVD, ROM, IR-ECO, etc
- 3DIC / Interposer – Power, Signal, Thermal Integrity
- Analog & Mixed-Signal Designs Power and Reliability
- RTL Power Analysis and Optimization
- Reliability Analysis: Electromigration, ESD, and Thermal
- Shift-left /In-design Analysis and Optimization
- Chip-Package-System Co-Simulation
Agenda
| Time | Session | Speakers | ||
| 9:00 am – 10:00 am | Registration + Hi-Tea | |||
| 10:00 am – 10:15 am | Welcome & Inauguration | Jai Pollayil Senior Director & Global Semiconductor AE Head Ansys |
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| 10:15 am – 10:45 am | Industry Keynote | Balajee Sowrirajan Corporate EVP & MD Samsung Semiconductor India Research |
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| 10:45 am – 11:15 am | Ansys Keynote | John Lee General Manager and Vice President Ansys |
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| 11:15 am – 11:30 am | Tea/Coffee Break | |||
| Track 1: Advanced SOC Power Integrity & Reliability (Convention Hall) |
Track 2: Power-Signal-Thermal-ESD Integrity across RTL / Custom IP / IC / 3DIC (Tactic 5) |
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| Session | Speakers | Session | Speakers | |
| 11:30 am – 12:00 pm | Conquering IR ECO complexity with PrimeClosure Synopsys |
Raghavendra Swami Sadhu | Backside power delivery and advanced technology EM/IR analysis in Totem Intel |
Anil Dsouza |
| 12:00 pm – 12:30 pm | Maximizing IR signoff coverage using Sigma-AV and its benefit on PPA |
Sandeep Gajbhare | Comprehensive Electrical & Thermal integrity of Power Management IC using a new Integrated solution Texas Instruments |
Girish Bijjal |
| 12:30 pm – 1:00 pm | Accelerating Full Flat EMIR Sign-off of Multi-billion Instance Design using RedHawk-SC ROM (Reduced Order Model) Samsung Semiconductor India Research |
Raja Ramachandra Rao & Satyaki Mandal | Optimizing Standard cell library development flow using “ParagonX” – EDA tool for IC layout parasitics analysis NXP Semiconductors |
Ravi JN & Santhosh Kamatam |
| 1:00 om – 2:00 pm | Lunch Break | |||
| 2:00 pm – 2:30 pm | An efficient methodology for Multi-PVT EMIR analysis of Large SOCs NVIDIA |
Ramesh Aggarwal | Signal and Power Integrity analysis of Silicon Interposer for multi-chiplet integration Alphawave Semi |
Gangaraju M & Yadavalli Jagadeeswari |
| 2:30 pm – 3:00 pm | Accounting for IR Drop in Static Timing Analysis: A Path to Accurate Delay Estimation Intel |
Purushotham Reddy N & Manoj Varama S | Comprehensive Thermal Analysis of 3DIC design using Redhawk_SC-ElectroThermal (RHSC-ET Samsung |
Rishikanth Mekala & Abhishek Chinchani |
| 3:00 pm – 3:30 pm | Novel method of Vectorless IR Analysis for DFT MediaTek |
Arun CS | Accelerated ESD Sign-off with Pathfinder-SC: An Efficient and Scalable Approach |
Smaritha Kasukurthi |
| 3:30 pm – 4:00 pm | Optimizing Power Integrity with RHSC in Smart PDN Framework Qualcomm | Gaurav Jain & Rajender Nune | An Integrated Approach to Power Analysis & Optimization: Synergizing Emulation, RTL Design, and Physical Design AMD |
Neeraj Dwivedi |
| 4:00 pm – 4:30 pm | Robust techniques for IR prediction AMD |
Sayani Das | A Novel approach to cost-Efficient Hybrid Cloud Solutions with SeaScape’s DataLake and Micro-Resiliency ARM |
Chandrakumar A |
| 4:30 pm – 4:35 pm | Concluding Remarks | Concluding Remarks | ||
| 4:35 pm – 5:00 pm | Tea & Networking | |||