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ICCAD 2023
Hyatt Regency San Francisco Downtown SoMa 50 3rd Street, San Francisco, CA, United StatesJointly sponsored by IEEE and ACM, ICCAD is the premier forum to explore new challenges, present leading-edge innovative solutions, and identify emerging technologies in the electronic design automation research areas.… ICCAD 2023
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Mastering the Art of Managing IP, Chiplets, and Design Data
Join us on Wednesday, November 1st, for an eye-opening exploration of the inadequacy of common design data and IP management capabilities in the face of today’s intricate semiconductor chip designs. Discover… Mastering the Art of Managing IP, Chiplets, and Design Data
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Warp Speed Gate-Level Simulations with the Xcelium Multi-Core App
Are you ready to lead the way in gate-level digital simulations (GLS)? Dive into Cadence’s exclusive webinar and uncover the revolutionary Xcelium Multi-Core (MC) App—a game changer for GLS, allowing… Warp Speed Gate-Level Simulations with the Xcelium Multi-Core App
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RISC-V in Space
Omni Interlocken Hotel 5000 Interlocken boulevard, Broomfield, CO, United StatesJoin us for "RISC-V in... Space" on November 2, 2023, as we explore the exciting intersection of RISC-V, electronics design, and space! Agenda 9:30 AM - 10:00 AM Registration & Welcome 10:00… RISC-V in Space
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IR 2.0 – Building a New Paradigm for Power Integrity Design and Analysis
Cadence Design Systems, Building 5 2655 Seely Avenue, San Jose, CA, United StatesPower integrity (PI) is a major challenge for chip designers in the era of ubiquitous data, hyperconnectivity, and AI. Design size is exploding, and innovations in heterogenous integration are adding… IR 2.0 – Building a New Paradigm for Power Integrity Design and Analysis
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RISC-V Summit US
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesEach day, thousands of engineers around the world collaborate and contribute to advance RISC-V, the open-standard instruction set architecture that is defining the future of open computing. The RISC-V community… RISC-V Summit US
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RISC-V 101
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesThe RISC-V Instruction Set Architecture (ISA) is the future of computing. As an open standard, RISC-V is accelerating innovation and enabling unprecedented design freedom across every computing application. You've seen… RISC-V 101
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IESA AI Summit
Trident Hotel Hyderabad Hyderabad, IndiaExperience the unprecedented growth opportunities in the semiconductor and electronics industry, fueled by rapid advancements in Artificial Intelligence (AI). Embrace the paradigm shift from software-centric approaches to hardware-centric solutions, captivating… IESA AI Summit
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Proactive Data Center Management with Insight Platform
The DataCenter Insight Platform is an enterprise software solution that simplifies data center capacity management by making it proactive, rather than reactive. The platform is a database of data center… Proactive Data Center Management with Insight Platform
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TSMC 2023 Taiwan OIP Ecosystem Forum
Ambassador Hotel Hsinchu 0F, No.188, Sec. 2, Zhonghua Rd., Hsinchu City, TaiwanLearn About: Emerging advanced node design challenges and corresponding design flows and methodologies for N2, N3/N3E/N3P/N3AE, N4/N4P, N5/N5A, N6/N6e/N6RF/N7, N12e, and N22 Latest updates on TSMC 3DFabric™ chip stacking and… TSMC 2023 Taiwan OIP Ecosystem Forum
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Deep Dive into the UVM Register Layer: User-Defined Doors, Predictors, and Callbacks
This webinar focuses on three specific aspects of the UVM register layer that will help you to model in UVM some of the less obvious ways in which registers can… Deep Dive into the UVM Register Layer: User-Defined Doors, Predictors, and Callbacks
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CMOS Circuit Techniques for Wireline Transmitters Part I
Synopsys Webinar – Part I In this 3-part Synopsys webinar series, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like… CMOS Circuit Techniques for Wireline Transmitters Part I
12 events found.