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Memory Users Conference 2024
Advancements in memory technology are fueling rapid growth in big data applications across AI, 5G, Automotive, and HPC. These demanding applications create many challenges for memory designers. Some long-standing challenges… Memory Users Conference 2024
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Interactive SPICE Model Verification Platform ME-Pro
ME-Pro™ is a unified tool for designers, process developers, modeling engineers, and PDK engineer providing robust simulation and analysis capabilities for semiconductor device model verification and evaluation. This comprehensive platform… Interactive SPICE Model Verification Platform ME-Pro
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Memory Users Conference 2024 – China, Taiwan
Advancements in memory technology are fueling rapid growth in big data applications across AI, 5G, Automotive, and HPC. These demanding applications create many challenges for memory designers. Some long-standing challenges… Memory Users Conference 2024 – China, Taiwan
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Redefining Mobile Experiences with AI – Session 2
The Arm platform is providing the foundation for the next wave of AI smartphones and laptops. As AI models rapidly evolve, we’re seeing that software begins to outpace hardware, requiring… Redefining Mobile Experiences with AI – Session 2
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Electronic Design Process Symposium (EDPS) – 2024
SEMI 673 S. Milpitas Blvd, Milpitas, CA, United StatesEDPS 2024 is now taking shape. The place to be is once again SEMI, in Milpitas, and the dates are Thursday and Friday, Oct 3rd and 4th, 2024. Registration is… Electronic Design Process Symposium (EDPS) – 2024
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VC Formal Special Interest Group
Santa Clara Marriott 2700 Mission College Blvd, Santa Clara, CA, United StatesRegister for the Synopsys VC Formal Special Interest Group (SIG) event today. This event provides an opportunity for users, managers, and enthusiasts to stay connected with the latest formal verification… VC Formal Special Interest Group
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Signoff Special Interest Group
Santa Clara Marriott 2700 Mission College Blvd, Santa Clara, CA, United StatesJoin us at this year’s Synopsys Signoff SIG (Special Interest Group) event. Signoff is a critical quality control checkpoint in the chip development process, but design complexity and advance process… Signoff Special Interest Group
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AutoSens Europe 2024
Palau de Congressos Av. de la Reina Maria Cristina, Barcelona, SpainJoin us as we embark on an exciting new journey in the vibrant city of Barcelona! From 8-10 October 2024, we will unite the AutoSens community at the Palau de… AutoSens Europe 2024
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PCB West 2024
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesFor more than 30 years PCB West has trained designers, engineers, fabricators and, lately, assemblers on making printed circuit boards for every product or use imaginable. More than 2,000 designers,… PCB West 2024
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Accelerating DFT verification sign-off with the Questa DFT Verification Platform
Siemens EDA 46871 Bayside Parkway, Building B, Fremont, CA, United StatesAccelerating DFT verification sign-off with the Questa DFT Verification Platform This seminar will update you on technologies and techniques you can adopt to increase your DFT verification productivity today. Specifically,… Accelerating DFT verification sign-off with the Questa DFT Verification Platform
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Cocotb 2.0: Modernize your testbenches for even more productivity
Cocotb 2.0 is the latest major version of cocotb, ironing out many quirks that have accumulated over the years. With only small changes to your testbenches, you can benefit from… Cocotb 2.0: Modernize your testbenches for even more productivity
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The Development and Evolution of Verilog & SystemVerilog
Abstract: SystemVerilog is a super next-generation Verilog with a fancy marketing name. SystemVerilog leveraged many of its features from other languages and methodologies. Class-based capabilities, constrained random testing (CRT), and… The Development and Evolution of Verilog & SystemVerilog
12 events found.