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How to Reduce Thousands of False Errors in 15 Minutes
Analyzing electrical errors across an IP or a SoC at top level, can be a painful and long process, often requiring extensive setup time and hundred of hours to distinguish real issues from false positives. To address this challenge, Aniah developed OneCheck, a formal analysis tool capable of detecting 100% of electrical errors at the… How to Reduce Thousands of False Errors in 15 Minutes
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Ensuring my Design Verification is ISO26262 Compliant
Cadence, Bengaluru Sarjapur Outer Ring Road, Bengaluru, IndiaWith the widespread of the modern automobiles, run and regulated by automotive ECUs, the need for advanced safety features has also become inevitable. And this is why today modern vehicles are required to adhere to the safety standards listed within the Automotive Safety Integrity Level (ASIL).In this DVClub meeting our speakers will share best practices… Ensuring my Design Verification is ISO26262 Compliant
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Synopsys Virtual Prototyping Day 2024
Join us at Virtual Prototyping Day 2024 to hear about the latest deployed virtual prototyping innovations. This event highlights applications from around the world using the latest virtual prototyping technology, covering applications from automotive, AI, and data center domains. Industry leaders will share their experiences with the latest techniques and methodologies using virtual prototypes for… Synopsys Virtual Prototyping Day 2024
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IEEE SMC-IT/SCC 2024
Computer History Museum 1401 N. Shoreline Blvd, Mountain View, CA, United StatesThe International Conference on Space Mission Challenges for Information Technology (SMC-IT) and the Space Computing Conference (SCC) gather system designers, engineers, computer architects, scientists, practitioners, and space explorers with the objective of advancing information technology, and the computational capability and reliability of space missions. The forums will provide an excellent opportunity for fostering technical interchange… IEEE SMC-IT/SCC 2024
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Maximize Productivity with Deep Insights into PPA Trajectories
The digital chip design flow carries with it an enormous wealth of untapped information regarding the health and status of your SoC design. The ability to efficiently mine this data provides chip designers with comprehensive visibility and actionable insights to uncover PPA opportunities. This webinar will introduce you to Synopsys Design.da, the industry’s first comprehensive data-visibility… Maximize Productivity with Deep Insights into PPA Trajectories
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Efficient Way to UVM Constraint Randomization Debug
Become skilled at the art of UVM randomization debugging! Date: Wednesday, July 17, 2024 Time: 10:00am PDT | 1:00pm EDT This webinar equips you with effective strategies to tackle randomization-related errors within your UVM verification environment. We'll explore the power of Cadence's Verisium Debug, a tool designed to simplify the debugging process. What You Will Learn Practical… Efficient Way to UVM Constraint Randomization Debug
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Enhancing Manufacturing Test Flows with Synopsys VC Z01X
Leveraging functional patterns is crucial for achieving high defect coverage and reducing defective parts per million (DPPM) levels. Synopsys VC Z01X fault simulator offers enhanced fault coverage in manufacturing test flows, complementing ATPG tools like Synopsys TestMAX ATPG. In this presentation we will delve into unique coverage scenarios, such as resets and clocks blocked during ATPG mode. We'll… Enhancing Manufacturing Test Flows with Synopsys VC Z01X
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SNUG India 2024
Sheraton Grand Bengaluru Whitefield Bengaluru, IndiaSince 1991, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Software. Today, as the electronics industry’s largest user conference, SNUG brings together over 12,000 Synopsys tool and technology users across North America, Europe, Asia, and Japan. In addition to peer-reviewed technical presentations and insightful keynotes from… SNUG India 2024
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ITC India 2024
Radisson Blu Outer King Road, Bengaluru, IndiaInternational Test Conference is the world’s premier venue dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, design-for-test, design-for-manufacturing, silicon debug, manufacturing test, system test, diagnosis, reliability and failure analysis, and back to process and design improvement. At ITC India, design, test, and yield professionals can confront challenges… ITC India 2024
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30th Siemens Xcelerator Technology Innovation Awards
Join us as we name the winners of the most prestigious design contest in PCB — the 30th Siemens Xcelerator Technology Innovation Awards! During this live event, we will announce winners in multiple categories representing a wide variety of design types. Hear from leading industry experts as they discuss features that make these printed circuit… 30th Siemens Xcelerator Technology Innovation Awards
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Simulating AMD’s next-gen Versal Adaptive SoC devices using Questasim
Versal Adaptive SoC, a revolutionary adaptable platform developed by AMD, integrates several key components such as the AI Engine (AIE), Processing System (PS), Programmable Logic (PL), Network on Chip (NoC), and a diverse array of specialized IPs. This innovative platform facilitates the efficient execution of intricate algorithms spanning from machine learning to high-performance computing tasks.… Simulating AMD’s next-gen Versal Adaptive SoC devices using Questasim
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Chiplets: Building the Future of SoCs
Chiplets, also known as heterogeneous multi-die systems, are increasingly seen as the future of System on Chips (SoCs). They offer a solution to meet the growing demands of high-performance computing in various industries, particularly fueled by the widespread adoption of AI technology. However, while the concept of using chiplets to construct larger chips to overcome… Chiplets: Building the Future of SoCs
12 events found.