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Formal 101 – Exhaustive Scoreboarding and Data Integrity Verification Made Easy
Verifying the correct passage of data through a DUT in constrained-random simulation is easy to do for basic I/O cases – data loss, obvious corruption, and 1-1 data passage. But what about verifying out-of-order cases? Or intermittently dropped bytes? Granted, a testbench can be written to look out for these issues, but as the layers… Formal 101 – Exhaustive Scoreboarding and Data Integrity Verification Made Easy
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AI Everywhere Forum
From data centers, through edge accelerators to endpoint devices: Artificial intelligence (AI) Applications range from large scale analysis of medical data and online retail recommendation engines, to robotics and computer vision, to sensor fusion in the tiniest sensor nodes. The infusion of AI techniques into so many areas of computing is changing compute paradigms across… AI Everywhere Forum
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Agile Planning for SoC Design
Missed milestones, lack of traceability, and costly respins. These are examples of what you risk if you do not take planning seriously during semiconductor design. A rock-solid planning process in the SOC Design process is a must. At the same time, the era of innovation is changing the way teams organize their work. Driven by… Agile Planning for SoC Design
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Verification Day 2021
This virtual event provides an opportunity to stay informed about the latest innovations, techniques and methodologies in verification hardware and software. This 2-day event will share experiences and insights from users solving tough verification challenges using Synopsys solutions. This year’s event will have a special focus on technology trends and case studies spanning simulation, static,… Verification Day 2021
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MIPI DevCon 2021
A Virtual Event MIPI DevCon 2021 will be held 28-29 September, at 07:00-11:00 (PDT), bringing developers and engineers an online forum for training and education on MIPI specifications in mobile and beyond. The two-day program will feature technical sessions and member demos focused on application examples, use cases and in-depth discussions of key MIPI specifications in mobile… MIPI DevCon 2021
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Exploring Andes’ NX27V Vector Processor Instructions
Join Dr. Thang Tran, Principal Architect of Andes Technology Corp. and veteran of high-performance computing (HPC), on September 29, 2021, at 09:00 AM PDT for the last in his four-part masterclass series on demystifying the RISC-V Vector Extension. In this session, Dr. Tran presents examples using vector instructions based on Andes NX27V. He discusses NX27V performance,… Exploring Andes’ NX27V Vector Processor Instructions
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Common Challenges when Designing IoT PCBs – And How to Solve Them with Cadence
While IoT devices may seem simple to the end users (which is good), the electrical design complexity of these devices is often very high. Designers are required to work with limited board space while functionality and speed requirements continue to increase. These tight spaces, combined with the required highspeed signaling, leads to increased susceptibility to… Common Challenges when Designing IoT PCBs – And How to Solve Them with Cadence
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IP Based Digital Design Management that Goes Beyond the Basics
oin us on Thursday, September 30th to learn why common design management capabilities are not enough and what next generation capabilities are needed for IP based digital design management. Register Today! Here’s what you can learn: Complete digital design management checklist Tagging, branching, and merging Project BOM and IP conflicts Logistics: The webinar will be… IP Based Digital Design Management that Goes Beyond the Basics
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Avoiding SoC Security Threats – What Verification Engineers Should Know
Thursday, September 30, 2021 | 11:00 -11:30 a.m. PDT The development of secure systems is of paramount importance in this age of software intensive electronic systems. Security weaknesses in the SoC hardware can lead to vulnerabilities that may be exploited later on by malicious software. These challenging problems must be addressed pre-silicon and require rigorous… Avoiding SoC Security Threats – What Verification Engineers Should Know
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Scalable HPC platform and memory expansion techniques using Die-to-Die and LPDDR subsystems
With advanced packaging and interface solutions, it is possible to connect multiple CPU clusters (near or far) and share external memory resources among them. We will review some of the IPs required to build such a platform and recommend applications that can benefit from it. This webinar will be useful to designers, architects, and application… Scalable HPC platform and memory expansion techniques using Die-to-Die and LPDDR subsystems
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Digital Design Technology Symposium
A Must-Attend Event HPC, 5G, AI, Automotive: market segments like these are presenting new challenges to ASIC and SoC designers. Synopsys is focused on delivering a continuous stream of innovative solutions with future-proof technologies to address issues such as greater energy efficiency, improved power-performance-area, faster time to market, functional safety, security, and yield optimization. The… Digital Design Technology Symposium
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DesignCon Digital
This online event from the producers of DesignCon features an education program with on-demand webinars presented by a standout speaker list, suppliers with easy-to-find products and services, and multiple matchmaking and networking opportunities – with the quality you’ve come to expect from a DesignCon event. All of our DesignCon Digital education and information presented will… DesignCon Digital
12 events found.