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Avoiding SoC Security Threats – What Verification Engineers Should Know

September 30 @ 11:00 am - 11:30 am PDT

Avoiding SoC Security Threats – What Verification Engineers Should Know

Thursday, September 30, 2021 | 11:00 -11:30 a.m. PDT

The development of secure systems is of paramount importance in this age of software intensive electronic systems. Security weaknesses in the SoC hardware can lead to vulnerabilities that may be exploited later on by malicious software. These challenging problems must be addressed pre-silicon and require rigorous methodology combined with technology to provide increased security assurance.

 

Security assurance requires a full product life cycle approach. In this joint webcast, Synopsys and Tortuga will present a solution for security verification to enable the adoption of a Hardware Security Development Lifecycle (HSDL) to achieve pre-silicon security signoff.

 

You will learn how the Tortuga methodology and products for HSDL together with the Synopsys Verification Continuum® platform enable the analysis of security threats for long software scenarios with fast turn-around-time.

 

Target audience: Engineers working with Synopsys VCS® simulation and ZeBu® emulation system who want to extend their knowledge into security sign-off.

Details

Date:
September 30
Time:
11:00 am - 11:30 am PDT
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Synopsys
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