AI/ML
How to Overcome the Pain Points of AI/ML Hardware Design
Join Achronix for a live Webinar December 16th: 10-11 AM Pacific and Recorded On-Demand After the Event AI/ML hardware faces three common pain points: memory bandwidth, computational throughput and on-chip data movement. Next-generation FPGA technology includes a 2D network on chip, GDDR6 memory interfaces and high performance machine learning processors, which present new capabilities to… Read More »How to Overcome the Pain Points of AI/ML Hardware Design
Memory Bandwidth Races Higher with HBM3
With the formal release of the HBM3 specification, memory bandwidth for AI/ML and HPC shifts to a higher gear. Terabytes of bandwidth are possible using HBM3’s 2.5D/3D architecture. Join memory expert Frank Ferro as he discusses what changes come with the new generation of HBM, and how the Rambus HBM3 memory subsystem can help designers… Read More »Memory Bandwidth Races Higher with HBM3
59th DAC
Moscone Center 747 Howard Street, San Francisco, CA, United StatesThe Design Automation Conference (DAC) is the premier event devoted to the design and design automation of electronic systems and circuits. DAC focuses on the latest methodologies and technology advancements in electronic design. Get ready for 59th DAC returning to San Francisco, California this July 10-14 at the Moscone West Center. Join researchers, designers, practitioners,… Read More »59th DAC
CAD for Assurance: Panel 5: Hardware Assurance vs. AI: Friend or Foe?
Moderators: Ankur Srivastava (U. of Maryland) and Swarup Bhunia (U. of Florida) Panelists: - Mike Borza, Synopsys - Brian Night, Microsoft - Pompei Len Orlando, Air Force Research Lab (AFRL) - Antonio de la Serna, Siemens - Samuel M Weber, Office of Naval Research (ONR) 90-min panel Assurance of electronic hardware against diverse security and… Read More »CAD for Assurance: Panel 5: Hardware Assurance vs. AI: Friend or Foe?