AI/ML
How to Overcome the Pain Points of AI/ML Hardware Design
Join Achronix for a live Webinar December 16th: 10-11 AM Pacific and Recorded On-Demand After the Event AI/ML hardware faces three common pain points: memory bandwidth, computational throughput and on-chip data movement. Next-generation FPGA technology includes a 2D network on chip, GDDR6 memory interfaces and high performance machine learning processors, which present new capabilities to… Read More »How to Overcome the Pain Points of AI/ML Hardware Design
Memory Bandwidth Races Higher with HBM3
With the formal release of the HBM3 specification, memory bandwidth for AI/ML and HPC shifts to a higher gear. Terabytes of bandwidth are possible using HBM3’s 2.5D/3D architecture. Join memory expert Frank Ferro as he discusses what changes come with the new generation of HBM, and how the Rambus HBM3 memory subsystem can help designers… Read More »Memory Bandwidth Races Higher with HBM3
59th DAC
Moscone Center 747 Howard Street, San Francisco, CA, United StatesThe Design Automation Conference (DAC) is the premier event devoted to the design and design automation of electronic systems and circuits. DAC focuses on the latest methodologies and technology advancements in electronic design. Get ready for 59th DAC returning to San Francisco, California this July 10-14 at the Moscone West Center. Join researchers, designers, practitioners,… Read More »59th DAC
CAD for Assurance: Panel 5: Hardware Assurance vs. AI: Friend or Foe?
Moderators: Ankur Srivastava (U. of Maryland) and Swarup Bhunia (U. of Florida) Panelists: - Mike Borza, Synopsys - Brian Night, Microsoft - Pompei Len Orlando, Air Force Research Lab (AFRL) - Antonio de la Serna, Siemens - Samuel M Weber, Office of Naval Research (ONR) 90-min panel Assurance of electronic hardware against diverse security and… Read More »CAD for Assurance: Panel 5: Hardware Assurance vs. AI: Friend or Foe?
DVClub Europe – AI/ML in Verification
This is to inform you that the next DVClub Europe meeting takes place on Tuesday 17th October with a theme of "AI/ML in Verification". This DVClub consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to verification. Agenda (BST) 12:00 Welcome and Introduction - Mike Bartley, Senior Vice President -… Read More »DVClub Europe – AI/ML in Verification
DVClub India – Using AI/ML in Design Verification
Cadence, Bengaluru Sarjapur Outer Ring Road, Bengaluru, IndiaThis DVClub consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to verification. Venue – Cadence Design System, Bengaluru & Online Time Session 15:00 GMT Welcome and introduction - Mike Bartley, Tessolve 15:00 GMT Cadence 16:00 GMT Tessolve 16:30 GMT TBD 17:00 GMT Close About DVClub The principal… Read More »DVClub India – Using AI/ML in Design Verification
ISQED Symposium 2024
Seven Hills Conference Center 800 Font Blvd, San Francisco, CA, United StatesA pioneer and leading interdisciplinary conference, the 25thInternational Symposium on Quality Electronic Design (ISQED'24) accepts and promotes original and unpublished papers related to the topics shown below. ISQED'24 theme is AI/ML& Electronic Design, Hardware Security, Quantum Computing, 3D Integration, and IoT. Authors are invited to submit papers in following topics (please visit the website for… Read More »ISQED Symposium 2024
TechNES FPGA Front Runner Event
New Mills Wotton-under-Edge, United KingdomThe FPGA Front Runners event will be hosted by Renishaw at their venue in Wotton-under-Edge. The event will focus on “Using AI in development and product for FPGA”. If you are interested in speaking at this event please email mike.bartley@techworks.org.uk Topics for talks: What AI support is being built into the FPGA fabrics? How are… Read More »TechNES FPGA Front Runner Event
SEE, MAPLD 2024
Marriott La Jolla 4240 La Jolla Village Drive, La Jolla, CA, United StatesOur workshop will feature content including, but not limited to, the following areas: Artificial Intelligence & Machine Learning (AI / ML) Continuing Education & Workforce Development Designing with Field Programmable Gate Arrays (FPGAs) / Systems on a Chip (SoCs) / New Devices FPGA & SoC Assurance Guidelines and Standards On-Orbit Experiments & Model Validation Radiation… Read More »SEE, MAPLD 2024
Applying Artificial Intelligence in Fab Technology Co-Optimization
The common approach to optimize a fabrication process involves process and fab engineers creating and setting up Design of Experiments (DoEs) using a trial-and-error approach. This approach often leads to costly iterations since wafer fabrication is both expensive and time-consuming. Typically, it can take weeks to months of experimentation, depending on what process parameters are… Read More »Applying Artificial Intelligence in Fab Technology Co-Optimization
Future of Memory and Storage – 2024
Santa Clara Convention Center 5001 Great America Parkway, Santa Clara, CA, United StatesFMS: the Future of Memory and Storage is an all-inclusive international memory and storage showcase. It is the event for the memory and storage industry. It is the one-stop place to catch up on the latest technologies, see the hottest products, and learn about what's happening and where the latest trends are heading. FMS is now… Read More »Future of Memory and Storage – 2024
MLCAD Symposium 2024
Snowbird 9385 Snowbird Center Trail, Sandy, UT, United StatesThe symposium focuses on Machine Learning (ML) for all aspects of CAD and electronic system design. The symposium is sponsored by both the ACM Special Interest Group on Design Automation (SIGDA) and the IEEE Council on Electronic Design Automation (CEDA). The symposium program will have keynote and invited speakers in addition to technical presentations. MLCAD… Read More »MLCAD Symposium 2024