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CAD for Assurance: Panel 5: Hardware Assurance vs. AI: Friend or Foe?
August 12 @ 11:00 am - 12:00 pm EDT
Moderators: Ankur Srivastava (U. of Maryland) and Swarup Bhunia (U. of Florida)
– Mike Borza, Synopsys
– Brian Night, Microsoft
– Pompei Len Orlando, Air Force Research Lab (AFRL)
– Antonio de la Serna, Siemens
– Samuel M Weber, Office of Naval Research (ONR)
Assurance of electronic hardware against diverse security and trust issues has become a complex, challenging problem. On one hand, the explosion of design complexity demands a highly sophisticated design and verification process. On the other, the hardware life cycle for both A SIC and COTS (e.g., FPGA, microcontroller, etc.) components, increasingly involves a multitude of trust issues, requiring new thinking in system design and verification that can address the underlying lack of trust. AI techniques have shown great promises in mitigating these issues– from rapid exploration of viable attack space to detection of anomalous design artifacts. While the power of AI/ML is poised to make a transformative impact on hardware assurance, the research community has also identified assurance issues with AI/ML hardware themselves. In particular, their vulnerability against malicious manipulations, information leakage, and other attacks has created major concerns. This panel will examine the crucial challenge of hardware assurance in the modern supply chain ecosystem, evolving role of AI/ML in hardware assurance, and discuss their interdependence/conflicts.