AI
Optimized Chip Design with Main Processors and AI Accelerators
Presented by Paul Karazuba, VP of Marketing, Expedera & John Min, Director of Field Application Engineering, Andes Technology About this talk As AI capability is beginning large-scale deployment into edge devices, many wonder about the decision to use a specialized AI accelerator, rather than simply using the systems main processor. In this first of two… Read More »Optimized Chip Design with Main Processors and AI Accelerators
Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)
• Do you need to estimate the power advantage of implementing an AI algorithm on an accelerator? • Do you need to size the AI accelerator for existing and future AI requirements? • Would it be beneficial if you knew the latency advantage between ARM, RISC, DSP and Accelerator in deploying AI tasks? This webinar… Read More »Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)
59th DAC
Moscone Center 747 Howard Street, San Francisco, CA, United StatesThe Design Automation Conference (DAC) is the premier event devoted to the design and design automation of electronic systems and circuits. DAC focuses on the latest methodologies and technology advancements in electronic design. Get ready for 59th DAC returning to San Francisco, California this July 10-14 at the Moscone West Center. Join researchers, designers, practitioners,… Read More »59th DAC
Design Automation Conference, 2022
Moscone Center 747 Howard Street, San Francisco, CA, United StatesThe Design Automation Conference (DAC) is recognized as the premier event for the design and design automation of electronic chips to systems. DAC offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors. The conference is sponsored by the Association for Computing Machinery (ACM) and the Institute of Electrical… Read More »Design Automation Conference, 2022
AI-Driven Verification: Saving Time with Verdi Regression Debug Automation
Analyzing the thousands of failures from daily regression runs is a manual, tedious, and error-prone process. The process can significantly impact quality-of-results, time-to-results and cost-of-results. The Synopsys Verdi® Regression Debug Automation (RDA) is an artificial intelligence (AI) driven verification technology for automating the process of finding the root causes of failures in the design under… Read More »AI-Driven Verification: Saving Time with Verdi Regression Debug Automation
FPGAs for AI and AI for FPGAs
Artificial Intelligence (especially Deep Learning) is rapidly becoming the cornerstone of numerous applications, creating an ever-increasing demand for efficient Deep Learning (DL) processing. FPGAs provide massive parallelism, while being flexible and easily configurable, and also fast and power efficient. These unique properties make them appealing for DL acceleration in both data center and edge use… Read More »FPGAs for AI and AI for FPGAs
The Dawn of AI Revolution in Chip Design
Abstract: We are at the dawn of an AI revolution for every human activity including chip design. The AI revolution in chip design is absolutely necessary because of key macro trends influencing chip design and would further accelerate the AI revolution in all other fields. In this talk I will start with my personal journey… Read More »The Dawn of AI Revolution in Chip Design
DVCon Europe 2022
Holiday Inn Munich - City Centre Hochstraße 3, Munich, GermanyThe Design and Verification Conference & Exhibition Europe (DVCon Europe) is the premier European technical conference on system, software, design, verification, validation or integration. It is a place where the latest methodologies and technologies for the industrial use of tools, languages, and standards for integrated and embedded systems and products are shared and discussed. The… Read More »DVCon Europe 2022
Achieve Optimal PPA Targets Using AI-Driven Technology
Complexity brought on by advanced process nodes have opened the door to challenges in achieving optimal power, performance, and area (PPA). Manual methods are no longer viable given shrinking market windows. The need to drive for better results faster is increasing, and traditional methods cannot keep pace often taking months of tuning using 100s of… Read More »Achieve Optimal PPA Targets Using AI-Driven Technology
20th International Conference on IC Design and Technology (ICICDT)
University of Tokyo 7 Chome-3-1 Hongo, Tokyo, Japan2023 ICICDT is the twentieth edition (20th) in the series of the International Conference on IC Design and Technology, organized since 2004. 2023 ICICDT will be co-organized and held at the University of Tokyo, Tokyo, Japan from September 25-27, 2023. Design and technology co-optimization (DTCO) plays a critical role in the era of big data… Read More »20th International Conference on IC Design and Technology (ICICDT)
CMOS Circuit Techniques for Wireline Transmitters Part I
Synopsys Webinar – Part I In this 3-part Synopsys webinar series, we will present how hyperscale data centers are going through a paradigm shift with the advent of technologies like Artificial Intelligence (AI) and edge compute requiring hyperscale data centers to support exponential growth of data volume. This volume of network traffic demands an increase… Read More »CMOS Circuit Techniques for Wireline Transmitters Part I
Introducing Ansys AI: A New Chapter in Engineering Simulation
Join us to learn more about the AI and Simulation Revolution in this upcoming webinar. We're revolutionizing engineering simulation with the power of Artificial Intelligence with SimAI, AnsysGPT, and Ansys AI+. Overview At Ansys, we are revolutionizing engineering simulation with the power of Artificial Intelligence. Our AI-augmented simulation technology is a game-changer, bringing unprecedented speed,… Read More »Introducing Ansys AI: A New Chapter in Engineering Simulation