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Essential Steps to Simplify VHDL Testbenches Using OSVVM

This “Getting Started” webinar focuses on the first, essential steps you need to take when looking to improve your VHDL testbench approach. In this webinar we examine transaction-based testing, self-checking tests, messaging, reports, and Open Source VHDL Verification Methodology (OSVVM) helper utilities.   The “transaction” in transaction-based testing is just a fancy word for an… Read More »Essential Steps to Simplify VHDL Testbenches Using OSVVM

High-Performance RTL Simulation Workflow with Vivado and Active-HDL

Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility, acceleration capability, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs).… Read More »High-Performance RTL Simulation Workflow with Vivado and Active-HDL

High-Performance RTL Simulation Workflow with Quartus and Active-HDL

Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility, acceleration capability, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs).… Read More »High-Performance RTL Simulation Workflow with Quartus and Active-HDL

High-Performance RTL Simulation Workflow with Libero and Active-HDL

Based on recent industry research, the FPGA market was valued at approximately USD 7.5 Billion in 2023, with an expected compound annual growth rate (CAGR) of around 10% by 2032. More and more engineers will be adopting FPGAs due to their versatility, acceleration capability, power efficiency and lower non-recurring engineering (NRE) costs (compared to ASICs).… Read More »High-Performance RTL Simulation Workflow with Libero and Active-HDL

Making a Structured VHDL Testbench – A Demo for Beginners

Abstract: This demonstrated tutorial is intended for designers and verification engineers who want to learn to make better and more structured testbenches. This session will show you what is needed for any good testbench, irrespective of its complexity. We will make a testbench from scratch for a simple VHDL module and do the following: Add… Read More »Making a Structured VHDL Testbench – A Demo for Beginners

FPGA Conference Europe

NH München Ost Conference Center Einsteinring 20, Munich, Aschheim, Germany

The FPGA Conference Europe, organized by ELEKTRONIKPRAXIS and the FPGA training center PLC2, is Europe's leading specialist conference for programmable logic devices. The conference focusses on user-oriented, practically applicable solutions that developers can quickly integrate into their own everyday work. In increasingly AI-driven cloud data centres, in telecommunications and many other high-performance applications, Field Programmable… Read More »FPGA Conference Europe

Why Should Our Team be Using VHDL + OSVVM for Verification?

Abstract: This is a high-level presentation that identifies the key aspects of a modern verification methodology and shows how to achieve them with OSVVM. This is a great presentation to share with your management about why OSVVM (and OSVVM training) is important for your team. Description: Developing and deploying a verification methodology can be costly… Read More »Why Should Our Team be Using VHDL + OSVVM for Verification?

Using OSVVM’s AXI4 Verification Components: Pt 1 Creating the AXI4 Testbench / Test Harness

European Session Abstract: This “Getting Started” presentation is for engineers who need to use the OSVVM AXI4 verification components (VCs) in their testbenches. Part 1 of this presentation provides a detailed walkthrough of creating a testbench environment that uses AXI4 VCs. AXI4 VCs are probably the most complex VCs in the OSVVM library. This complexity… Read More »Using OSVVM’s AXI4 Verification Components: Pt 1 Creating the AXI4 Testbench / Test Harness

DVCon Japan 2024

TKP Garde CIty Premium - Shinagawa Takanawa, Tokyo TKP Garden City Premium, Tokyo, Japan

The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees… Read More »DVCon Japan 2024

Static and Dynamic CDC Verification of AXI4 Stream-based IPs

The AXI4 Stream protocol is used as a standard interface to exchange data between connected IPs within FPGA designs. For crossing clock domains, the AXI4 Stream interconnect is based on switches capable of transferring data to another asynchronous clock domain. The alternative solution is a dual-port AXI4 Stream IP, capable of changing clock domains when… Read More »Static and Dynamic CDC Verification of AXI4 Stream-based IPs

Navigating COTS-IP in DO-254: Strategies for Safe and Efficient FPGA Design

The integration of COTS-IP (Commercial Off-The-Shelf Intellectual Property) components in FPGA-based Avionics systems can significantly speed up development and enhance performance. However, it also introduces unique challenges, as these components may not align with the strict aviation development assurance standards required for DO-254 compliance. This webinar will guide you through the process of balancing the… Read More »Navigating COTS-IP in DO-254: Strategies for Safe and Efficient FPGA Design