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ALINT-PRO
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Verifying AXI Interconnects with ALINT-PRO and Riviera-PRO
AXI has become the most popular internal bus protocol with today’s FPGA and SoC FPGA designs. ALINT-PRO enables FPGA designers to extract, review and statically verify AXI bus interfaces. In… Verifying AXI Interconnects with ALINT-PRO and Riviera-PRO
LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)
Abstract: Today’s FPGAs and SoC FPGAs use various types of bus interconnect - such as AXI, APB, AHB, Avalon or Wishbone - for both internal (IP-level) and external communication. A… LIVE WEBINAR: How to Simplify the Verification of Bus Interfaces (US)