ASIC
How Designing a Custom ASIC Chip Will Help Scientists Detect Neutrinos From Outer Space
Join us on Thursday, November 3rd to learn how Lawrence Berkeley National Laboratory, Fermilab, and Brookhaven National Laboratory collaborated and designed a custom ASIC chip to run at extremely cold temperatures, so that it can detect neutrinos! Register Today! Here’s what you can learn: Why study neutrinos and how to detect them DUNE experiment –… How Designing a Custom ASIC Chip Will Help Scientists Detect Neutrinos From Outer Space
Latch-Up 2023
University of California, Santa Barbara Santa Barbara, CA, United StatesThe FOSSi Foundation is proud to announce Latch-Up, a conference dedicated to free and open source silicon to be held over the weekend of Friday, March 31 to Sunday, April 2, 2023 in Santa Barbara, California, USA. Latch-Up is a weekend of presentations and networking for the open source digital design community, much like its European sister conference ORConf. So… Latch-Up 2023
CHIPS Alliance – FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development
Google 237 Moffett Park Drive, Sunnyvale, CA, United StatesIP share and reuse is fundamental for efficient chip design. But in order to do this efficiently we need tools and methods. On the software side, the concept of package managers is widely used to build a product from many different sources, but chip designers often rely on ad-hoc solutions which tends to build up… CHIPS Alliance – FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development
Latest Innovations and Updates in ASICs
In this webinar Jeff DiCorpo & Matt Venn will delve into the latest ASIC developments, including the game-changing OpenFrame – a new Caravel version expanding your design possibilities by 50%. Topics Include: - OpenFrame - a new version of Caravel that gives 50% more area - GPIO configuration questions - The new cocotb testing framework… Latest Innovations and Updates in ASICs
DFT for chiplets & 3D ICs using Tessent Multi-die
3D IC (2.5D/3D) designs are on the rise. Design for Test (DFT) for chiplets must be general purpose so they can be tested stand alone and easy to test after assembly into 2.5D or 3D devices. In this webinar you will learn how to use Tessent Multi-die and still adhere to standards like IEEE 1149.1,… DFT for chiplets & 3D ICs using Tessent Multi-die
ORConf 2024
Gothenburg Gothenburg, SwedenOur 10th ORConf! The FOSSi Foundation is proud to announce the 10th installment of ORConf, a conference dedicated to free and open source silicon to be held over the weekend of Friday September 13 to Sunday September 15 in Gothenburg, Sweden. ORConf is a weekend of presentations and networking for the open source silicon community.… ORConf 2024