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DFT for chiplets & 3D ICs using Tessent Multi-die
April 30 @ 6:00 am - 7:00 am PDT
3D IC (2.5D/3D) designs are on the rise. Design for Test (DFT) for chiplets must be general purpose so they can be tested stand alone and easy to test after assembly into 2.5D or 3D devices. In this webinar you will learn how to use Tessent Multi-die and still adhere to standards like IEEE 1149.1, IEEE 1500, IEEE 1687, and IEEE 1838.
Who should attend:
- Anyone planning to implement chiplets, 2.5D/3D designs and would like to learn about design for test.
- DFT Engineers
- DFT Managers
- Design Engineers
- Test Engineers
- Project Managers for ASIC/design
What you will learn:
- How Tessent Multi-die will aid in 3D IC design for test
- Intro to what IEEE 1838 standard is and how Tessent solution can be used. Use of Tessent Streaming Scan Network (SSN) as flexible parallel port (FPP)
- How in 2.5D device, boundary scan-based interconnect test can be performed with Tessent Multi-die
Itamar Tsachi has more than 20 years of experience in the semiconductor industry and has collaborated with many local and international Siemens EDA customers on a wide range of solutions targeting DFT and RTL->GDSII flows. Before joining Mentor Graphics, Itamar ramped up IBM’s Physical Design Group in Israel developing SoCs using IBM’s leading-edge technology. Itamar was also a Physical Implementation Consultant and Leader at multiple startups like Mysticom, BrightCom technologies and Silicon Value, where he began his chip design career in a variety of roles, from Digital / Analog layout design to Place & Route and CAD development. Itamar holds one Patent” Placement Driving Routing (PDR) – “A method and apparatus for placement driven routing with a minimum number of changes in the placement.”