CHIPS Alliance – FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development

IP share and reuse is fundamental for efficient chip design. But in order to do this efficiently we need tools and methods. On the software side, the concept of package managers is widely used to build a product from many different sources, but chip designers often rely on ad-hoc solutions which tends to build up a maintenance cost and burden. Fortunately FuseSoC and Edalize exists to help. Being the most popular package manager for IP cores, there are already hundreds of FuseSoC-compatible IP cores available. Most high-profile open source silicon projects have already adopted FuseSoC or are looking at doing so, and it is being increasingly used inside small and large companies for development of proprietary systems as well. With support for almost 40 different EDA tool flows it covers a wide range of work flows from synthesis to simulation to formal verification. Sounds great, doesn’t it? It sure does, and this presentation will take you through the basics of FuseSoC to help you get started, using VeeRwolf, the CHIPS Alliance-governed reference platform for the VeeR family of CPU cores as an example, and looks beyond this to how FuseSoC can help you focus on your core business instead of your cores.