Cadence
CadenceCONNECT – Photonics Event
Cadence Design Systems, Bldg 10 2655 Seeley Avenue, San Jose, CA, United StatesJoin Cadence in person for the 8th annual CadenceCONNECT Photonics event and workshop on February 7 – 8, 2024, to discuss the increasingly important role of photonics in enabling AI transformation. We all know photonics is essential for communication, but how about computing? What are its advantages and challenges? Which applications are best suited? How… Read More »CadenceCONNECT – Photonics Event
Seamless SI/PI Signoff of Allegro PCB Designs Driven by In-Design Analysis
Signal and power integrity (SI/PI) are top priorities for engineers designing today’s high-speed, high-density PCBs. Easy-to-use in-design analysis directly integrated into the Allegro PCB design environment uncovers SI/PI issues early in the design process, leading to faster signoff of designs. With analysis shifting left in the design cycle, design teams can achieve efficient signoff of… Read More »Seamless SI/PI Signoff of Allegro PCB Designs Driven by In-Design Analysis
ISSCC 2024
San Francisco Marriot Marquis 780 Mission Street, San Francisco, CA, United StatesThe International Solid-State Circuits Conference is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design and application to maintain technical currency, and to network with leading experts.
DVClub India – Using AI/ML in Design Verification
Cadence, Bengaluru Sarjapur Outer Ring Road, Bengaluru, IndiaThis DVClub consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to verification. Venue – Cadence Design System, Bengaluru & Online Time Session 15:00 GMT Welcome and introduction - Mike Bartley, Tessolve 15:00 GMT Cadence 16:00 GMT Tessolve 16:30 GMT TBD 17:00 GMT Close About DVClub The principal… Read More »DVClub India – Using AI/ML in Design Verification
Intel Foundry Services (IFS) Direct Connect
San Jose Convention Center 150 W San Carlos Street, San Jose, CA, United StatesJoin us virtually to hear Pat Gelsinger and Stu Pann discuss progress in delivering the world's first Systems Foundry for the AI Era to meet the ever-expanding demands of the Siliconomy. The keynote will feature special appearances by U.S. Secretary of Commerce Gina M. Raimondo and Microsoft Chairman and CEO Satya Nadella. Be sure to stick… Read More »Intel Foundry Services (IFS) Direct Connect
SPIE Advanced Lithography + Patterning
San Jose Convention Center 150 W San Carlos Street, San Jose, CA, United StatesAttend and hear research, challenges, and breakthroughs as you gather with colleagues in San Jose Join other leading researchers who are solving challenges in optical and EUV lithography, patterning technologies, metrology, and process integration for semiconductor manufacturing and adjacent applications. Five days of exciting content and connecting with your community Plenary talks Technical presentations Networking… Read More »SPIE Advanced Lithography + Patterning
DVCon USA 2024
The DoubleTree by Hilton 2050 Gateway Place, San Jose, CA, United StatesThe Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. The focus of this highly technical conference is on the practical aspects of these technologies and their use in leading-edge projects to encourage attendees… Read More »DVCon USA 2024
Efficient Design Methodology for 112G Interface Compliance
As 112G+ data transfer becomes the new normal, companies risk schedule delays unless they improve the efficiency of their multi-board design methodology. An efficient design methodology looks at signal and power integrity early and often as the design progresses. In addition, with the precision required to meet 112G compliance, companies can take extra steps to… Read More »Efficient Design Methodology for 112G Interface Compliance
What’s New About Virtuoso Layout Suite?
Accelerate Layout Creation with Automated Place and Route in Virtuoso Studio How can you cut down custom layout implementation from days to minutes? Custom device-level automated place and route (APR) for advanced nodes has very different requirements than mature node chip assembly routing. With our new unified APR flow-based user interface integrating the various automation… Read More »What’s New About Virtuoso Layout Suite?
GOMACTech 2024
Embassy Suites by Hilton Charleston Convention Center, Charleston, SC, United StatesGOMACTech was established primarily to review developments in microcircuit applications for government systems. Established in 1968, the conference has focused on advances in systems being developed by the Department of Defense and other government agencies and has been used to announce major government microelectronics initiatives such as VHSIC and MIMIC, and provides a forum for… Read More »GOMACTech 2024
Virtuoso – Save on Signoff Effort with In-Design DRC and Fill
Virtuoso Layout Suite has pioneered in-design DRC checking and fixing in the layout editor. However, many of you have realized that the lack of completeness of rules in the techfile has caused many violations to fall through the cracks and are discovered later during signoff. An in-design DRC checking with signoff rule decks often comes… Read More »Virtuoso – Save on Signoff Effort with In-Design DRC and Fill
DVClub Europe: Latest VHDL Verification Techniques
This DVClub focuses on the latest verification techniques in VHDL including UVVM and OSVVM Agenda (GMT) 13:00 Welcome and Introduction – Mike Bartley, Tessolve 13:00 Epsen Tallaksen, EmLogic - Get the right FPGA quality through efficient Specification Coverage (aka Requirement Coverage) 13:30 Jim Lewis, SynthWorks - OSVVM in a NutShell, VHDL’s #1 Verification Methodology 14:00 Close Additional… Read More »DVClub Europe: Latest VHDL Verification Techniques