DSP
Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)
• Do you need to estimate the power advantage of implementing an AI algorithm on an accelerator? • Do you need to size the AI accelerator for existing and future AI requirements? • Would it be beneficial if you knew the latency advantage between ARM, RISC, DSP and Accelerator in deploying AI tasks? This webinar… Read More »Balancing Performance and Power in adding AI Accelerators to System-on-Chip (SoC)
DSP IP for High Performance Sensor Fusion on an Embedded Budget
The growing use of a variety of sensors in edge devices – from wearables to virtual assistants to automotive radar/LiDAR – requires SoCs to have an optimal balance of DSP performance and low power/area. In addition, SoC developers must be able to easily scale their hardware architectures to handle a varying number of data streams… Read More »DSP IP for High Performance Sensor Fusion on an Embedded Budget
Formal Validation of a Datapath Pipelined Design with VC Formal
Finite Impulse Response (FIR) filters are widely used in communication, consumer electronics, and many other digital signal process (DSP) applications. A FIR filter includes a complex pipelined datapath based on arithmetic functions such as multipliers with its output at any given time depending on the previous state. Exhaustive verification of an FIR filter is important… Read More »Formal Validation of a Datapath Pipelined Design with VC Formal