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Formal Validation of a Datapath Pipelined Design with VC Formal

November 30 @ 10:00 am - 11:00 am PST

Synopsys, November 30, 2022

Finite Impulse Response (FIR) filters are widely used in communication, consumer electronics, and many other digital signal process (DSP) applications. A FIR filter includes a complex pipelined datapath based on arithmetic functions such as multipliers with its output at any given time depending on the previous state. Exhaustive verification of an FIR filter is important to catch all possible design issues. In this Synopsys webinar, we will showcase how to use Synopsys VC Formal DPV, a formal verification app for datapath validation, to accomplish the challenging verification tasks.

Speaker

Laureano Carrasco

Lead Application Engineer EU
Synopsys

Laureano Carrasco Costilla is a Lead Application Engineer for VC Formal at Synopsys based in Munich, Germany. His technical expertise and interests lie with Formal Verification, ESL design, AI/ML, emulation and prototyping. Laureano holds a MSc in Physics from UVa and a Master on Business Direction and Marketing by UNED, Spain.

Details

Date:
November 30
Time:
10:00 am - 11:00 am PST
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Organizer

Synopsys
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