HLS
Introduction to the Joules RTL Power Solution
Want to take a tour of this powerful power estimation tool and gear up so you understand the Joules flow? Join Cadence Training and Sr Principal Education Application Engineer Neha Joshi for this free technical Training Webinar. Built on a multi-threaded frame-based architecture, the Cadence® Joules™ RTL Power Solution delivers 20X faster time-based RTL power… Read More »Introduction to the Joules RTL Power Solution
Driving Low-Power Design with High-Level Synthesis
With the growth in computing at the edge driven by the explosion of battery-powered smart devices, designing for low power is mission-critical to product success. Numerous techniques, spanning all stages of design, are employed to reduce power. Since many of the low-power design techniques come at a cost in performance, the key design challenge continues… Read More »Driving Low-Power Design with High-Level Synthesis
FPGA Frontrunner Meet & Greet
Leonardo EH5 2XS, Edinburgh, United KingdomTechNES is pleased to announce the next FPGA Front Runners event – to he hosted by Leonardo at their venue in Edinburgh on March 29th, and will focus on FPGA Design using High Level Languages. The FPGA Front runners is all about bringing together the UK FPGA & ASIC design communities to discuss all things… Read More »FPGA Frontrunner Meet & Greet
An AI/ML Driven High-Level Synthesis Solution
High-Level Synthesis (HLS) tools yield better PPA when the "right set" of optimization constraints and tool settings are applied. Determining the right set of constraints and settings requires design and tool experience and exploration. AI/ML technology has proven highly effective at exploring the solution space and lowering the required tool expertise. This CadenceTECHTALK™ presents details on… Read More »An AI/ML Driven High-Level Synthesis Solution