In the latest generation of multiple processor SoCs, designers are adding cache-coherent agents beyond the multi-processor clusters, making it a complex verification challenge. System coherency needs to be maintained at various levels, beginning at the cluster level, and continuing, across the cache coherent interconnect and across chips through chip-to-chip gateways. The coherency protocol across interconnects… Read More »A Scalable Approach to 2X Faster Turnaround Time for Arm Neoverse N2 Core Design Verification