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A Scalable Approach to 2X Faster Turnaround Time for Arm Neoverse N2 Core Design Verification

November 17 @ 10:30 am - 11:30 am PST

Neoverse

In the latest generation of multiple processor SoCs, designers are adding cache-coherent agents beyond the multi-processor clusters, making it a complex verification challenge. System coherency needs to be maintained at various levels, beginning at the cluster level, and continuing, across the cache coherent interconnect and across chips through chip-to-chip gateways. The coherency protocol across interconnects can be AMBA 5, ACE, CHI, CCIX, or CXL. To ensure system level coherency is maintained, a robust cache-coherent checker is required which checks for rules across the system and reports failures on inconsistencies. In addition, the design also goes through multiple revisions adding another level of challenge which requires a scalable testbench that can be reused across projects and from IP to SoC.

 

In this webcast we will talk about how the Synopsys Verification Continuum solution, spanning VCS, Verdi and Verification IP, helped reduce an Arm® Neoverse™ N2 core testbench bring-up time by 50%. We will also cover how using scalable protocol converters in the coherency checkers, enabled Arm to address the end-to-end challenges and measure the latency and throughput bottlenecks.

Speakers

Listed below are the industry leaders scheduled to speak.

Eric Sondhi

Sr. Product Manager, SoC Development Solutions
Arm

Eric is product manager for SoC Development solutions at Arm. Eric has worked with Arm’s lead partners and SoC designers around the world to employ cycle-accurate modeling technology and virtual prototype solutions for early SoC architecture, SW development, and system performance analysis.

Eric also has over 10 years’ experience designing enterprise-class storage stacks and device drivers for information infrastructure start-ups and best-in-breed storage providers including EMC, Dell, and DataGravity.

Satya Acharya

Sr. Manager, Applications Engineering
Synopsys

Satyapriya (Satya) Acharya is a Senior AE Manager at Synopsys, where he manages the use of Synopsys Verification IP for ARM AMBA protocols and verification automation technology with several key customers. He has strong expertise in AMBA based design verifications using SystemVerilog UVM. He has been involved in the development, verification and deployment of Synopsys Verification IP for the AMBA 3, AMBA 4 and AMBA 5 specifications. Satyapriya earned his Bachelor of Engineering degree from VSSUT, Orissa, India and has more than 17 years of experience in design and verification.

Details

Date:
November 17
Time:
10:30 am - 11:30 am PST
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Organizer

Synopsys
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