Riviera-PRO
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Verifying AXI Interconnects with ALINT-PRO and Riviera-PRO
AXI has become the most popular internal bus protocol with today’s FPGA and SoC FPGA designs. ALINT-PRO enables FPGA designers to extract, review and statically verify AXI bus interfaces. In… Verifying AXI Interconnects with ALINT-PRO and Riviera-PRO
System Simulation of Versal ACAP Designs
AVersal ACAP, developed by Xilinx/AMD, is a groundbreaking adaptable platform composed of AI Engine (AIE), Processing System (PS), Programmable Logic (PL), Network on Chip (NoC) and a wide range of… System Simulation of Versal ACAP Designs
Introduction to OpenCPI (US)
The Open Component Portability Infrastructure (OpenCPI) is an open source software (OSS) framework for developing and executing component-based applications on heterogeneous systems. By targeting heterogeneous systems, the framework supports development… Introduction to OpenCPI (US)