Siemens
Latest Past Events
Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
Gate-level simulations (GLS) are a crucial step in the verification of an ASIC/FPGA. GLS is used for verifying power-up, reset operation, timing, multi-cycle paths, and power estimation. However, GLS can… Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
GOMACTech 2024
Embassy Suites by Hilton Charleston Convention Center, CharlestonGOMACTech was established primarily to review developments in microcircuit applications for government systems. Established in 1968, the conference has focused on advances in systems being developed by the Department of… GOMACTech 2024
New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
Designers increasingly use complex reset signaling architectures to meet high-performance, low-latency, and low-power requirements. Specifically, independent reset domains are created by complex reset sequences, reset circuitry, and the intermixing of… New Advanced Techniques for Reset Domain Crossing (RDC) Analysis