New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

Designers increasingly use complex reset signaling architectures to meet high-performance, low-latency, and low-power requirements. Specifically, independent reset domains are created by complex reset sequences, reset circuitry, and the intermixing of IPs with different reset schemas, power-management domains, and security domains or functionality. This increase in reset signaling complexity is creating new RDC verification challenges that are straining “gen one” RDC solutions.
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In this webinar we will show new, advanced RDC techniques, methodology, and automation for:
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• How to hierarchically characterize and structure reset (and clock) domain models for rapid analysis and re-use of IP-level RDC information as the design grows
• AI/ML-based automation that pinpoints where to place synchronizers, and in parallel to aggressively minimize false positives (e.g. automatically minimizing “noise”)
• Creating custom synchronizers for proprietary synchronization styles
• Waiver management flows to efficiently address violations and waiver tracking throughout the project
• Considerations for low power designs with UPF

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What you will learn:

A short review of the basics of Clock and Reset Domain Crossing issues that may cause meta-stability, glitch or data coherency.
What’s the right methodology for a comprehensive RDC analysis?
Questa RDC solutions

Who should attend:

Design Engineers, CAD Engineers, Project Leads who are using/supporting static verification flows.
Working knowledge of Verilog, SystemVerilog, or VHDL will presumed.

Atul Sharma

Lead Product Engineer, Siemens EDA

Atul Sharma is Lead Product Engineer for Questa Static and Formal Solutions in Design Verification Technology Division of Siemens Electronic Design Automation (EDA) and is primarily responsible for CDC, RDC, SignOff CDC and Lint products. Atul has 16 years of experience in design and verification, design methodologies, technical marketing and applications engineering. Prior to Siemens EDA, Atul has held design verification role for a design company, and Product expert role in an EDA company, for multiple products covering different aspects of static and functional verification.

With 16 years of total experience, he has spent over a decade in customer facing role to solve Static Verification issues (CDC, RDC, Lint, DFT, Power Estimation/Reduction & Power Verification) and to create customer methodologies, use models for multiple EDA products.