Tessolve
Latest Past Events
Using AI in development and product for FPGA
Renishaw plc New Mills, Wotton-under-Edge, GloucestershireFPGA Front Runner - Using AI in development and product for FPGA How are they used? What input language is used and how does it find it’s way into the FPGA? How is the AI trained? Any use case example Agenda (GMT) Time Speaker Details 09.00 Arrival and registration 09:30 Pete Leonard, Renishaw Introduction to… Using AI in development and product for FPGA
Webinar 3: Tessolve AI assisted advanced DV Flow and Use cases
Webinar 3: Tessolve AI assisted advanced DV Flow and Use cases With the increasing importance of AI in engineering and the exciting potential for it’s use in Design Verification, Tessolve has been working on improving internal DV processes, with impressive reductions in both effort and costs, and with many clients to improve both efficiency and quality… Webinar 3: Tessolve AI assisted advanced DV Flow and Use cases
DVClub Europe – AI/ML in Verification
This DVClub will consider how we can save time and effort whilst improving time-to-market through the application of AI/ML to design verification. Agenda (GMT): Time Session Description Slides Videos 12.00 GMT Welcome and Introduction – Mike Bartley, Tessolve Mike Bartley,Tessolve 12.00 GMT Hardik Raina, Agnisys, Inc - Genetic Algorithms for Automated Verification from VCD Data. 12.20… DVClub Europe – AI/ML in Verification