UCIe
Protocol and Memory Interface Verification in the Shrinking World of 3DIC
Emerging 2.5D and 3DIC packaging technologies enable more design complexity, and bring some new verification challenges. We look at how to scale your verification capability to match and how to plan ahead for verification of die-to-die interconnect protocols such as UCIe and memory verification with HBM. Packaging technologies for 2.5D and 3DIC are becoming more… Read More »Protocol and Memory Interface Verification in the Shrinking World of 3DIC
Evaluating UCIe based multi-die architectures to meet timing and power constraints
Multi-die architectures have evolved from proprietary to industry standard UCIe. UCIe can accommodate the bulk of designs today from 8 Gbps per pin to 32 Gbps per pin for high-bandwidth applications from networking to Hyperscale data centers. To help your UCIe adoption journey, we present VisualSim Architect and the associated UCIe/PCIe6.0 IPs to explore and… Read More »Evaluating UCIe based multi-die architectures to meet timing and power constraints
Chiplet Summit
DoubleTree Hotel 2050 Gateway Place, San Jose, CA, United StatesThe First Annual Chiplet Summit is the show chip designers can’t miss if they want to stay competitive. They’ll get the scoop on ways to make their chiplets run faster, scale better, use less power, and be more flexible. This unique event gives attendees a place to network with peers, ask questions of the experts,… Read More »Chiplet Summit
Introduction to UCIe
UCIe™ — Universal Chiplet Interconnect Express™ — is an open industry standard founded by the leaders in semiconductors, packaging, IP suppliers, foundries, and cloud service providers to address customer requests for more customizable package-level integration. The newly formed UCIe Consortium fosters an open chiplet ecosystem by offering high-bandwidth, low-latency, power-efficient, and cost-effective on-package connectivity between… Read More »Introduction to UCIe
Requirements for Multi-Die System Success
Wednesday, May 24, 2023 and Thursday, May 25, 2023 The industry is moving to multi-die systems to benefit from the greater compute performance, increased functionality, and new levels of flexibility. Challenges for multi-die systems are exacerbated and require greater focus on a number of requirements such as early partitioning and thermal planning, die/package co-design, secure… Read More »Requirements for Multi-Die System Success
UCIe PHY Modeling and Simulation with XMODEL
Chiplets are emerging as a new way of building IC systems via heterogeneous integration, and Universal Chip Interconnect Express (UCIe) is one of the standards defining the interconnects among chiplets. This webinar presents the SystemVerilog models of a Universal Chiplet Interconnect Express (UCIe) interface, including both the analog circuits in the electrical layer and digital… Read More »UCIe PHY Modeling and Simulation with XMODEL