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Protocol and Memory Interface Verification in the Shrinking World of 3DIC
September 21, 2022 @ 8:00 am - 9:00 am PDT
Emerging 2.5D and 3DIC packaging technologies enable more design complexity, and bring some new verification challenges. We look at how to scale your verification capability to match and how to plan ahead for verification of die-to-die interconnect protocols such as UCIe and memory verification with HBM.
Packaging technologies for 2.5D and 3DIC are becoming more available and more accessible, with solutions addressing both the economics problem and the technical scalability challenge of building ever more complex SoCs. Standards are competing and emerging for interconnect protocols, memory interfaces, backplane-like and motherboard-like solutions within the IC package.
In this session, we take a look at how to scale your verification capability to match those designs, divide and conquer, and use the right abstractions to equip projects with high quality and faster time-to-market, and to equip design/verification engineers with scalable tools and solutions for verification. We will dive into the interface and memory protocols driving High Performance Compute innovation – PCIe Gen6, CXL, HBM3, and future UCIe, as well as important aspects of enabling scalability such as IDE security.
What You Will Learn:
- The challenges of verifying today’s advanced die-to-die interface and memory protocols
- The broad portfolio of Siemens EDA Verification IP solutions available today
- How our automated approach and flexible VIP can enable your productivity
Who Should Attend:
- Design & Verification Engineers & Managers and those interested in Protocol or Memory Interface verification
Verification IP Product Manager
Gordon Allan is Product Manager for Verification IP at Siemens EDA. Gordon was one of the authors of Accellera UVM, and he published the online UVM Cookbook on our Verification Academy site where it is appreciated by over 65,000 engineers today. Prior to joining the EDA industry he gained over 18 years of Design/Verification experience leading & developing SoC and complex protocol IP/VIP projects in several semiconductor companies, fabless startups, EDA and system houses. Gordon is based in Silicon Valley.
Verification Product Technologist
Joe Hupcey III is a part of the Siemens EDA Product Management team for Design & Verification Technologies; based in Siemens’ office in Silicon Valley, CA. He is responsible for the Formal product line of automated applications and advanced property checking. Prior to joining Siemens, Joe has held product management and marketing roles in several Electronic Design Automation (EDA) companies, for products that covered multiple aspects of hardware and software functional verification. Before transitioning into marketing, Joe worked as an electrical engineer in FPGA design, EDA tools for FPGAs and ASICs, and ASIC verification. Joe’s educational background includes BSEE, MSEE, and MBA degrees from Cornell University in Ithaca, NY.