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Evaluating UCIe based multi-die architectures to meet timing and power constraints
October 27 @ 10:00 am - 11:00 am PDT
Multi-die architectures have evolved from proprietary to industry standard UCIe. UCIe can accommodate the bulk of designs today from 8 Gbps per pin to 32 Gbps per pin for high-bandwidth applications from networking to Hyperscale data centers. To help your UCIe adoption journey, we present VisualSim Architect and the associated UCIe/PCIe6.0 IPs to explore and verify use cases and optimize the power, timing, throughput and functionality.
This Webinar looks at the system-wide view of performance and power in a UCIe multi-die SOC. We will be showcasing processor, data center and imaging use cases that combines various types of processing engines across PCIe and UCIe. This modeling effort will present the user with different performance and system architecture models and a guide on design aspects that optimizes for power efficiency, low latency, high bandwidth to transfer massive amounts of data, and error-free operation. Simulating multi-die system architectures with large payloads and multiple streaming protocols can be done in minutes, thus greatly expanding the usefulness of simulation.