In the semiconductor foundry business we all know that TSMC sits at the top, followed by: Samsung, UMC, GlobalFoundries and SMIC. So Intel wants back into this service business, and is slowly rebuilding its capabilities after a failed first attempt in the foundry business years ago. A foundry needs semiconductor IP and approved EDA tools flow, and these all come from outside of Intel. Today, we saw the first press from Intel Foundry Services with the launch of something called Accelerator, an Ecosystem Alliance.
The major EDA players all issued their own press releases, confirming that they’ve joined the alliance:
Semiconductor IP vendors are also showing their support for the alliance:
So it’s an ambitious reboot for IFS, yet I have several follow on questions:
- Do the EDA tool vendors have to qualify their specific tools for each Intel process node? When does that happen?
- Will the IP vendors have to do test tape outs to prove the worthiness of their building blocks? When will that happen?
- Who are the first customers of IFS, beyond the DOD/RAMP-C program, AWS and Qualcomm. When do we see actual silicon results?
- Will IFS hold technology road shows for their customers and prospects, like TSMC and Samsung do?
- What is the ideal IFS customer profile?
I’ve watched Intel Capital invest in EDA and IP companies for many years now, so it’s a smart move to invest another $1B in early-stage startups doing IC design. IFS offering x86, Arm and RISC-V cores makes sense, anything to keep the foundry full should be attractive. I’d like to see IFS use their own domain name, like intelfoundry.com, just to create some distance with intel.com.
Instead of spending $20B on a fab in Ohio, I would’ve setup a new Intel fab in Taiwan, as an incentive to attract local talent away from TSMC and help play catchup in process technology development.
Classical marketing theory says that it’s unwise to choose a frontal assault against established competitors, so IFS has to use some strategy of going after foundry customers in some narrower segments that they can defend and even dominate. It’s not really evident to me what this narrow market segment is that IFS is trying to serve that their competitors are not serving already.
Sure, I wish IFS much success, and Intel was the best hardware company that I ever worked at, so I’ll continue to watch the rollout in the coming months and years.
Samsung is talking about using equivalency checking and ML with Synopsys tools to design SoCs, the webinar is June 9th, 10AM PDT. https://marketingeda.com/event/5x-faster-equivalence-checking-with-formality-ml-driven-dpx/ #SemiEDA
At the Synopsys User Group meeting I learned about aging analysis from a CPU company, short blog at https://semiwiki.com/eda/312706-using-sta-with-aging-analysis-for-robust-ic-designs/ #SemiEDA #SemiWiki
ITherm 2022 is a conference for packaging engineers concerned about thermal issues, it's from May 31 - June 3, in sunny San Diego. #SemiEDA vendor: Cadence. https://marketingeda.com/event/itherm-2022/
Learn about SystemVerilog Assertions, there's a webinar from Doulos on June 1st, 10-11AM PDT. Become an expert in 60 minutes, uh, good luck. https://marketingeda.com/event/become-an-sva-expert-in-one-hour/ #SemiEDA
@findmewoeyes The best answer would come from an HSPICE AE, it's been too long since I last ran a SPICE circuit simulator.
Joseph Sawicki of Siemens EDA presented at User2User recently, and here's what I learned. #SemiEDA #SemiWiki
Joseph Sawicki of Siemens EDA at User2User - Semiwiki
I attended the annual user group meeting called User2User in…
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Photonic IC designers should attend the PIC International 2022 conference, June 28-29 in Brussels. #SemiEDA companies: Ansys, Cadence, Siemens EDA, Silvaco, Synopsys. https://marketingeda.com/event/pic-international-conference/
IC and package co-design is made possible with Cadence tools, find out more at the June 14th webinar, European times. https://marketingeda.com/event/increase-efficiency-and-reduce-risks-with-ic-and-package-co-design-flows/ #SemiEDA
Power device engineers want to be in Vancouver, BC to attend the IEEE ISPSD 2022 conference, it's May 22-25 this year, meeting in person. #SemiEDA vendors: Silvaco, Silicon Frontline https://marketingeda.com/event/ieee-ispsd-2022/ #SemiIP
Embedded software development benefits from using virtual prototypes, and Synopsys has a webinar on this, May 26th at 9AM PDT. https://marketingeda.com/event/turbo-charge-your-embedded-ci-cd-setup-using-virtual-prototypes/ #SemiEDA
@TudorTimi Uh, that was a deleterious side effect (aka bug). Sorry to hear about the #SemiEDA drama, but users are the Beta testers and QA department, obliged to pay an annual maintenance fee to have bugs fixed, eventually. The bigger your budget, the faster the fix.
How does embedded analytics help cybersecurity threat detection and mitigation? I found out how at the IP SoC Silicon Valley 2022 event in April. #SemiEDA #SemiIP #SemiWiki
Cybersecurity Threat Detection and Mitigation - Semiwiki
Every week in the technology trade press I am reading…
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Learn about automotive cybersecurity from Secure-IC at this May 24th webinar: Off-board and On-board, standards and technologies. https://marketingeda.com/event/automotive-cyber-security-off-board-and-on-board-standards-and-technologies/ #SemiIP
FPGA design and verification engineers interested in code, functional and specification coverage can learn something new at this Aldec webinar, May 19th, both US and European time slots. https://marketingeda.com/event/fpga-design-verification-code-functional-and-specification-coverage/ #SemiEDA
@arduissimo Are you on Strava? If so, follow me,
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@arduissimo Thanks, the donors have been generous in 2022. I've been cycling Saturday Century rides for a few years now, so the body is ready.
Tomorrow is the big day, I'm cycling 100 miles with friends to Reach The Beach, raising funds for the American Lung Association. Any donation amount is appreciated, and tax deductible. https://action.lung.org/site/TR/Cycle/ALAMP_Mountain_Pacific?px=7458379&pg=personal&fr_id=22051
Save $995.00 and attend this free FPGA workshop online, it's all about designing with the Versal ACAP from Xilinx, taught by Doulos, two half-days, May 24-25. https://marketingeda.com/event/versal-acap-workshop-online/ #SemiEDA #SemiIP
PCIe 6.0 uses PAM-4 signaling, so you'll need to have some SI/PI analysis to get it right. There's a Cadence webinar on this, May 19th, 10AM PDT. https://marketingeda.com/event/conquer-si-pi-challenges-and-reduce-time-to-signoff-for-pcie-6-0/ #SemiEDA
FPGA verification engineers can use VHDL and OSVVM as a new verification methodology. Learn more at this Aldec hosted webinar on May 26th, part one of four. https://marketingeda.com/event/better-fpga-verification-with-vhdl-osvvm-leading-edge-verification-for-the-vhdl-community/ #SemiEDA
Designing ethernet for automotive? Check out the 8th annual conference, Automotive Ethernet Congress, it's June 1-2, located in Munich, Germany. #SemiEDA vendors: Mirabilis, Siemens EDA. https://marketingeda.com/event/automotive-ethernet-congress/
Test engineers have a one week event in Barcelona, Spain, sponsored by the IEEE, it's the European Test Symposium. May 23-27, look for: Advantest, Cadence, FormFactor, HiSilicon, Infineon, Siemens EDA, Synopsys, Teradyne. https://marketingeda.com/event/european-test-symposium-2022/ #SemiEDA
Analog IC layout is tedious and error prone, so why not try something with more automation. There's a webinar on May 24th from Pulsic, and it helps Virtuoso users get to layout much quicker. https://marketingeda.com/event/a-faster-path-to-analog-layout/ #SemiEDA
#SemiIP vendors will attend the Embedded Vision Summit: Arm, Cadence, CEVA DSP, Efinix, Flex Logix, Synopsys. Dozens of other vendors too. It's May 17-18 in Santa Clara, CA. https://marketingeda.com/event/embedded-vision-summit/
Sensor fusion is popular for edge devices, yet there are so many DSP IP choices to make this happen. Find out what Synopsys has to offer at this webinar on May 24th, 10AM PDT. https://marketingeda.com/event/dsp-ip-for-high-performance-sensor-fusion-on-an-embedded-budget/ #SemiIP
