In the semiconductor foundry business we all know that TSMC sits at the top, followed by: Samsung, UMC, GlobalFoundries and SMIC. So Intel wants back into this service business, and is slowly rebuilding its capabilities after a failed first attempt in the foundry business years ago. A foundry needs semiconductor IP and approved EDA tools flow, and these all come from outside of Intel. Today, we saw the first press from Intel Foundry Services with the launch of something called Accelerator, an Ecosystem Alliance.
The major EDA players all issued their own press releases, confirming that they’ve joined the alliance:
Semiconductor IP vendors are also showing their support for the alliance:
So it’s an ambitious reboot for IFS, yet I have several follow on questions:
- Do the EDA tool vendors have to qualify their specific tools for each Intel process node? When does that happen?
- Will the IP vendors have to do test tape outs to prove the worthiness of their building blocks? When will that happen?
- Who are the first customers of IFS, beyond the DOD/RAMP-C program, AWS and Qualcomm. When do we see actual silicon results?
- Will IFS hold technology road shows for their customers and prospects, like TSMC and Samsung do?
- What is the ideal IFS customer profile?
I’ve watched Intel Capital invest in EDA and IP companies for many years now, so it’s a smart move to invest another $1B in early-stage startups doing IC design. IFS offering x86, Arm and RISC-V cores makes sense, anything to keep the foundry full should be attractive. I’d like to see IFS use their own domain name, like intelfoundry.com, just to create some distance with intel.com.
Instead of spending $20B on a fab in Ohio, I would’ve setup a new Intel fab in Taiwan, as an incentive to attract local talent away from TSMC and help play catchup in process technology development.
Classical marketing theory says that it’s unwise to choose a frontal assault against established competitors, so IFS has to use some strategy of going after foundry customers in some narrower segments that they can defend and even dominate. It’s not really evident to me what this narrow market segment is that IFS is trying to serve that their competitors are not serving already.
Sure, I wish IFS much success, and Intel was the best hardware company that I ever worked at, so I’ll continue to watch the rollout in the coming months and years.
@ESDAlliance @nanettecollins I worked with Mark Templeton at Silicon Compilers, Inc. in the 80s, so thanks for honoring his work to grow the #SemiIP business.
Learn all about prototyping for SoC and #SemiIP development at this Cadence webinar, October 26, 10AM PDT. Details, https://marketingeda.com/event/protium-enterprise-prototyping-higher-productivity-lower-costs/ #SemiEDA
Just added MyHDL (Python as a hardware description and verification language) to the EDA Open Source and Free Tools Wiki at https://semiwiki.com/wikis/industry-wikis/eda-open-source-tools-wiki/. #SemiEDA #SemiIP #SemiWiki
Clear communication means avoiding double-negatives, unlike this recent technical quote:
Looking for an Open Source tool for schematic capture that outputs VHDL, Verilog or SPICE? Check out XSCHEM, just added to our Wiki list, https://semiwiki.com/wikis/industry-wikis/eda-open-source-tools-wiki/ #SemiEDA #SemiWiki
Synopsys is in Hawaii at the Applied Superconductivity Conference, October 23-28. Conference details, https://marketingeda.com/event/the-applied-superconductivity-conference/ #SemiEDA
Just added CflexHDL and PipelineC to the EDA Open Source and Free Tools Wiki, #SemiEDA #SemiWiki
EDA Open Source and Free Tools Wiki - Semiwiki
SYSTEM PandA-bambu - framework for research in high-level synthesis and…
semiwiki.com
Synopsys just announced a new tool, PrimeClosure, for smarter ECO flows. Blog at #SemiEDA #SemiWiki
New ECO Product – Synopsys PrimeClosure - Semiwiki
New EDA product launches are always an exciting time, and…
semiwiki.com
The 48th International Symposium for Testing and Failure Analysis is in-person, October 30 - November 3, held in Pasadena, CA. See what Siemens EDA is showing on reversible scan diagnosis. Details, https://marketingeda.com/event/istfa-2022/ #SemiEDA
@Thalia_IP_Reuse I’ve been using #SemiIP to disambiguate IP, as many industries unrelated to semiconductor also use IP.
Custom IC designers can learn about using post-layout circuit sizing optimization at this webinar, hosted by MunEDA, October 4th. Why do manual transistor sizing anymore? #SemiEDA #SemiIP #SemiWiki
Webinar: Post-layout Circuit Sizing Optimization - Semiwiki
My IC design career started out with manually sizing transistors…
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How do you manage to create your 3D IC system-level netlist? Siemens EDA has an approach for 2.5D and 3D IC projects. #SemiEDA #SemiIP #SemiWiki
3D IC – Managing the System-level Netlist - Semiwiki
I just did a Google search for
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Andes Technology hosts the RISC-V Con on October 18th, in San Jose. Speakers from: Intel Foundry Services, Sonical, IAR Systems, Green Hills Software, Crypto Quantique. Details, https://marketingeda.com/event/risc-v-con/ #SemiIP #SemiEDA
The annual RISC-V Summit is in-person, December 13-14, San Jose. #SemiIP and #SemiEDA from: Andes Technology, Codasip, Imagination, Imperas, Microchip, SiFive. Details, https://marketingeda.com/event/risc-v-summit/
PCB designers, engineers and fabricators gather in Santa Clara for the annual PCB West conference and exhibition, October 4-7. Expecting 2,500 people, details, https://marketingeda.com/event/pcb-west-2022/ #SemiEDA
Engineers designing MMIC, RFIC and RF SiP will be interested in this Cadence webinar, October 18th, 9AM-10AM PT. Details, https://marketingeda.com/event/cadence-further-streamlines-mmic-rfic-and-rf-sip-design-workflows/ #SemiEDA #SemiIP
Synopsys has a symposium on photonic IC design, it's virtual, October 19th, from 8:00-11:30AM PT. Details, https://marketingeda.com/event/accelerating-innovation-in-photonic-ic-design/ #SemiEDA
Here's a smart way to connect all of those chiplets together, Bunch of Wires (BoW), like: Arm, Cisco, Meta, Google, JCET, d-Matrix, Blue Cheetah, Analog Port. Blog, #SemiWiki #SemiIP
Die-to-Die Interconnects using Bunch of Wires (BoW) - Semiwiki
Chiplets are a popular and trending topic in the semiconductor…
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@iamPrabhava My wife kicked the Google Assistant speaker from the living room for exactly the same reason, as it would randomly just start answering without any key phrase being spoken.
The 2022 IEEE EDPS is all set, October 6-7, in Milpitas. Sponsors: Ansys, Cadence, CEDA, Intel, Synopsys. Details, https://marketingeda.com/event/2022-ieee-electronic-design-process-symposium-edps/ #SemiEDA #SemiIP
European semiconductor professionals can attend the ESSCIRC 2022, 19-22 September, in Milan. Details, https://marketingeda.com/event/esscirc-2022/ #SemiEDA #SemiIP #SemiFoundry
Synopsys users in Europe, starting planning to attend SNUG Europe, October 17-18 in Munich. Details, https://marketingeda.com/event/snug-europe/ #SemiEDA #SemiIP
Learn how to efficiently model your system: automotive network, radar, semiconductor. Webinar by Mirabilis on September 29th, both America and Asia/Europe time zones. Details, https://marketingeda.com/event/architecture-exploration-of-automotive-networks-radars-and-semiconductors/ #SemiEDA
Semiconductor professionals near Germany may be interested in the GlobalFoundries Technology Summit, held in Dresden on September 28-29. #SemiEDA
vendors: Synopsys, Cadence, Siemens EDA, Ansys. Details, https://marketingeda.com/event/global-foundries-technology-summit-emea/ #Foundry #SemiIP
Cadence logic simulation users should attend this webinar on Xcelium Apps, it could help you save some verification time. September 21 at 9AM, PDT. https://marketingeda.com/event/xcelium-apps-everything-you-need-in-the-simulation-metaverse/ #SemiEDA
