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Transcending RTL – At DAC This Year

Transcending RTL

I first met Steve Hoover a few years ago online, then at a DAC. We both worked at Intel, so his startup company Redwood EDA caught my attention. I’ve watched over the decades as Verilog and VHDL grew up to be the two dominant RTL languages for both design and verification, and many have tried to get to the next level of abstraction for SoC design. Steve organized a session at DAC this year, Transcending RTL, so I invite you to consider attending virtually.

Since the introduction of RTL into the design process, silicon has scaled, under the forces of Moore’s Law, by five orders of magnitude! Circuit design at today’s scale faces fundamentally different challenges than RTL was intended to address. Abstraction must play a more significant role, with tools owning more responsibility for design details. Leverage and reuse are essential. RTL no longer provides a viable methodology to carry us forward. The industry has pinned its hopes on SystemC and high-level synthesis to answer the call. While these offer clear benefits, they also have drawbacks that have led to slow adoption. In this session, you will learn about several promising design methodologies, languages, and tool capabilities you will not find in the mainstream. Perhaps one of them will strike a chord with issues faced in your organization.

When: July 23, 10:30AM – Noon

Where: DAC online


 Speaker:Jan Kuper – QBayLogic B.V., Enschede, The Netherlands
 Author:Jan Kuper – QBayLogic B.V., Enschede, The Netherlands
1.2Fluid Pipelines and Live Flow with Pyrope
 Speaker:Jose Renau – Univ. of California, Santa Cruz, CA
 Author:Jose Renau – Univ. of California, Santa Cruz, CA
1.3Transaction-Level Design with TL-Verilog
 Speaker:Steven Hoover – Redwood EDA, Shrewsbury, MA
 Author:Steven Hoover – Redwood EDA, Shrewsbury, MA
Transcending RTL

2 thoughts on “Transcending RTL – At DAC This Year”

  1. The simulation model in EDA itself can be an implementation,
    with a little help from the CPU ? And, what about vice-versa
    ( hardware accelerators and the like ) ?

    1. At this DAC session three experts talk about their approaches at raising the SoC design abstraction above traditional RTL coding, so I invite you to attend the session and ask the same question.

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